1 // SPDX-License-Identifier: ISC
2 /*
3  * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
4  * processor reference design.
5  *
6  * This platform has the codename "Richfield".
7  *
8  * This machine is based on a 533 MHz IXP425.
9  */
10 
11 /dts-v1/;
12 
13 #include "intel-ixp42x.dtsi"
14 #include "intel-ixp4xx-reference-design.dtsi"
15 #include <dt-bindings/input/input.h>
16 
17 / {
18 	model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
19 	compatible = "intel,ixdp425", "intel,ixp42x";
20 	#address-cells = <1>;
21 	#size-cells = <1>;
22 
23 	soc {
24 		bus@c4000000 {
25 			flash@0,0 {
26 				compatible = "intel,ixp4xx-flash", "cfi-flash";
27 				bank-width = <2>;
28 				/* Enable writes on the expansion bus */
29 				intel,ixp4xx-eb-write-enable = <1>;
30 				/* 16 MB of Flash mapped in at CS0 */
31 				reg = <0 0x00000000 0x1000000>;
32 
33 				partitions {
34 					compatible = "redboot-fis";
35 					/* Eraseblock at 0x0fe0000 */
36 					fis-index-block = <0x7f>;
37 				};
38 			};
39 		};
40 
41 		/* EthB */
42 		ethernet@c8009000 {
43 			status = "okay";
44 			queue-rx = <&qmgr 3>;
45 			queue-txready = <&qmgr 20>;
46 			phy-mode = "rgmii";
47 			phy-handle = <&phy0>;
48 
49 			mdio {
50 				#address-cells = <1>;
51 				#size-cells = <0>;
52 
53 				phy0: ethernet-phy@0 {
54 					reg = <0>;
55 				};
56 
57 				phy1: ethernet-phy@1 {
58 					reg = <1>;
59 				};
60 			};
61 		};
62 
63 		/* EthC */
64 		ethernet@c800a000 {
65 			status = "okay";
66 			queue-rx = <&qmgr 4>;
67 			queue-txready = <&qmgr 21>;
68 			phy-mode = "rgmii";
69 			phy-handle = <&phy1>;
70 		};
71 	};
72 };
73