1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "aspeed-g4.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
5 
6 / {
7 	model = "Quanta Q71L BMC";
8 	compatible = "quanta,q71l-bmc", "aspeed,ast2400";
9 
10 	aliases {
11 		i2c14 = &i2c_pcie2;
12 		i2c15 = &i2c_pcie3;
13 		i2c16 = &i2c_pcie6;
14 		i2c17 = &i2c_pcie7;
15 		i2c18 = &i2c_pcie1;
16 		i2c19 = &i2c_pcie4;
17 		i2c20 = &i2c_pcie5;
18 		i2c21 = &i2c_pcie8;
19 		i2c22 = &i2c_pcie9;
20 		i2c23 = &i2c_pcie10;
21 		i2c24 = &i2c_ssd1;
22 		i2c25 = &i2c_ssd2;
23 		i2c26 = &i2c_psu4;
24 		i2c27 = &i2c_psu1;
25 		i2c28 = &i2c_psu3;
26 		i2c29 = &i2c_psu2;
27 	};
28 
29 	chosen {
30 		stdout-path = &uart5;
31 		bootargs = "console=ttyS4,115200 earlycon";
32 	};
33 
34 	memory@40000000 {
35 		reg = <0x40000000 0x8000000>;
36 	};
37 
38 	reserved-memory {
39 		#address-cells = <1>;
40 		#size-cells = <1>;
41 		ranges;
42 
43 		vga_memory: framebuffer@47800000 {
44 			no-map;
45 			reg = <0x47800000 0x00800000>; /* 8MB */
46 		};
47 	};
48 
49 	leds {
50 		compatible = "gpio-leds";
51 
52 		heartbeat {
53 			gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
54 		};
55 
56 		power {
57 			gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
58 		};
59 
60 		identify {
61 			gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
62 		};
63 	};
64 
65 	iio-hwmon {
66 		compatible = "iio-hwmon";
67 		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
68 			<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
69 			<&adc 8>, <&adc 9>, <&adc 10>;
70 	};
71 
72 	iio-hwmon-battery {
73 		compatible = "iio-hwmon";
74 		io-channels = <&adc 11>;
75 	};
76 
77 	i2c1mux: i2cmux {
78 		compatible = "i2c-mux-gpio";
79 		#address-cells = <1>;
80 		#size-cells = <0>;
81 
82 		/* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
83 		i2c-parent = <&i2c1>;
84 	};
85 };
86 
87 &fmc {
88 	status = "okay";
89 	flash@0 {
90 		status = "okay";
91 		label = "bmc";
92 		m25p,fast-read;
93 #include "openbmc-flash-layout.dtsi"
94 	};
95 };
96 
97 &spi {
98 	status = "okay";
99 	pinctrl-names = "default";
100 	pinctrl-0 = <&pinctrl_spi1_default>;
101 
102 	flash@0 {
103 		status = "okay";
104 		m25p,fast-read;
105 		label = "pnor";
106 	};
107 };
108 
109 &pinctrl {
110 	pinctrl-names = "default";
111 	pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
112 			&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
113 };
114 
115 &p2a {
116 	status = "okay";
117 	memory-region = <&vga_memory>;
118 };
119 
120 &ibt {
121 	status = "okay";
122 };
123 
124 &lpc_ctrl {
125 	status = "okay";
126 };
127 
128 &lpc_snoop {
129 	status = "okay";
130 	snoop-ports = <0x80>;
131 };
132 
133 &mac0 {
134 	status = "okay";
135 	pinctrl-names = "default";
136 	pinctrl-0 = <&pinctrl_rmii1_default>;
137 	use-ncsi;
138 };
139 
140 &mac1 {
141 	status = "okay";
142 	pinctrl-names = "default";
143 	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
144 };
145 
146 &uart1 {
147 	status = "okay";
148 };
149 
150 &uart5 {
151 	status = "okay";
152 };
153 
154 &i2c0 {
155 	status = "okay";
156 };
157 
158 &i2c1 {
159 	status = "okay";
160 
161 	/* temp2 inlet */
162 	tmp75@4c {
163 		compatible = "ti,tmp75";
164 		reg = <0x4c>;
165 	};
166 
167 	/* temp3 */
168 	tmp75@4e {
169 		compatible = "ti,tmp75";
170 		reg = <0x4e>;
171 	};
172 
173 	/* temp1 */
174 	tmp75@4f {
175 		compatible = "ti,tmp75";
176 		reg = <0x4f>;
177 	};
178 
179 	/* Baseboard FRU */
180 	eeprom@54 {
181 		compatible = "atmel,24c64";
182 		reg = <0x54>;
183 	};
184 
185 	/* FP FRU */
186 	eeprom@57 {
187 		compatible = "atmel,24c64";
188 		reg = <0x57>;
189 	};
190 };
191 
192 &i2c2 {
193 	status = "okay";
194 
195 	/* 0: PCIe Slot 2,
196 	 *    Slot 3,
197 	 *    Slot 6,
198 	 *    Slot 7
199 	 */
200 	i2c-mux@74 {
201 		compatible = "nxp,pca9546";
202 		reg = <0x74>;
203 		#address-cells = <1>;
204 		#size-cells = <0>;
205 		i2c-mux-idle-disconnect;  /* may use mux@77 next. */
206 
207 		i2c_pcie2: i2c@0 {
208 			#address-cells = <1>;
209 			#size-cells = <0>;
210 			reg = <0>;
211 		};
212 
213 		i2c_pcie3: i2c@1 {
214 			#address-cells = <1>;
215 			#size-cells = <0>;
216 			reg = <1>;
217 		};
218 
219 		i2c_pcie6: i2c@2 {
220 			#address-cells = <1>;
221 			#size-cells = <0>;
222 			reg = <2>;
223 		};
224 
225 		i2c_pcie7: i2c@3 {
226 			#address-cells = <1>;
227 			#size-cells = <0>;
228 			reg = <3>;
229 		};
230 	};
231 
232 	/* 0: PCIe Slot 1,
233 	 *    Slot 4,
234 	 *    Slot 5,
235 	 *    Slot 8,
236 	 *    Slot 9,
237 	 *    Slot 10,
238 	 *    SSD 1,
239 	 *    SSD 2
240 	 */
241 	i2c-mux@77 {
242 		compatible = "nxp,pca9548";
243 		#address-cells = <1>;
244 		#size-cells = <0>;
245 		reg = <0x77>;
246 		i2c-mux-idle-disconnect;  /* may use mux@74 next. */
247 
248 		i2c_pcie1: i2c@0 {
249 			#address-cells = <1>;
250 			#size-cells = <0>;
251 			reg = <0>;
252 		};
253 
254 		i2c_pcie4: i2c@1 {
255 			#address-cells = <1>;
256 			#size-cells = <0>;
257 			reg = <1>;
258 		};
259 
260 		i2c_pcie5: i2c@2 {
261 			#address-cells = <1>;
262 			#size-cells = <0>;
263 			reg = <2>;
264 		};
265 
266 		i2c_pcie8: i2c@3 {
267 			#address-cells = <1>;
268 			#size-cells = <0>;
269 			reg = <3>;
270 		};
271 
272 		i2c_pcie9: i2c@4 {
273 			#address-cells = <1>;
274 			#size-cells = <0>;
275 			reg = <4>;
276 		};
277 
278 		i2c_pcie10: i2c@5 {
279 			#address-cells = <1>;
280 			#size-cells = <0>;
281 			reg = <5>;
282 		};
283 
284 		i2c_ssd1: i2c@6 {
285 			#address-cells = <1>;
286 			#size-cells = <0>;
287 			reg = <6>;
288 		};
289 
290 		i2c_ssd2: i2c@7 {
291 			#address-cells = <1>;
292 			#size-cells = <0>;
293 			reg = <7>;
294 		};
295 	};
296 };
297 
298 &i2c3 {
299 	status = "okay";
300 
301 	/* BIOS FRU */
302 	eeprom@56 {
303 		compatible = "atmel,24c64";
304 		reg = <0x56>;
305 	};
306 };
307 
308 &i2c4 {
309 	status = "okay";
310 };
311 
312 &i2c5 {
313 	status = "okay";
314 };
315 
316 &i2c6 {
317 	status = "okay";
318 };
319 
320 &i2c7 {
321 	status = "okay";
322 
323 	/* 0: PSU4
324 	 *    PSU1
325 	 *    PSU3
326 	 *    PSU2
327 	 */
328 	i2c-mux@70 {
329 		compatible = "nxp,pca9546";
330 		reg = <0x70>;
331 		#address-cells = <1>;
332 		#size-cells = <0>;
333 
334 		i2c_psu4: i2c@0 {
335 			#address-cells = <1>;
336 			#size-cells = <0>;
337 			reg = <0>;
338 
339 			psu@59 {
340 				compatible = "pmbus";
341 				reg = <0x59>;
342 			};
343 		};
344 
345 		i2c_psu1: i2c@1 {
346 			#address-cells = <1>;
347 			#size-cells = <0>;
348 			reg = <1>;
349 
350 			psu@58 {
351 				compatible = "pmbus";
352 				reg = <0x58>;
353 			};
354 		};
355 
356 		i2c_psu3: i2c@2 {
357 			#address-cells = <1>;
358 			#size-cells = <0>;
359 			reg = <2>;
360 
361 			psu@58 {
362 				compatible = "pmbus";
363 				reg = <0x58>;
364 			};
365 		};
366 
367 		i2c_psu2: i2c@3 {
368 			#address-cells = <1>;
369 			#size-cells = <0>;
370 			reg = <3>;
371 
372 			psu@59 {
373 				compatible = "pmbus";
374 				reg = <0x59>;
375 			};
376 		};
377 	};
378 
379 	/* PDB FRU */
380 	eeprom@52 {
381 		compatible = "atmel,24c64";
382 		reg = <0x52>;
383 	};
384 };
385 
386 &i2c8 {
387 	status = "okay";
388 
389 	/* BMC FRU */
390 	eeprom@50 {
391 		compatible = "atmel,24c64";
392 		reg = <0x50>;
393 	};
394 };
395 
396 &vuart {
397 	status = "okay";
398 };
399 
400 &wdt2 {
401 	status = "okay";
402 };
403 
404 &adc {
405 	status = "okay";
406 };
407 
408 &pwm_tacho {
409 	status = "okay";
410 
411 	pinctrl-names = "default";
412 	pinctrl-0 = <&pinctrl_pwm0_default
413 		&pinctrl_pwm1_default
414 		&pinctrl_pwm2_default
415 		&pinctrl_pwm3_default>;
416 
417 	fan@0 {
418 		reg = <0x00>;
419 		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
420 	};
421 
422 	fan@1 {
423 		reg = <0x01>;
424 		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
425 	};
426 
427 	fan@2 {
428 		reg = <0x02>;
429 		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
430 	};
431 
432 	fan@3 {
433 		reg = <0x03>;
434 		aspeed,fan-tach-ch = /bits/ 8 <0x03>;
435 	};
436 
437 	fan@4 {
438 		reg = <0x00>;
439 		aspeed,fan-tach-ch = /bits/ 8 <0x04>;
440 	};
441 
442 	fan@5 {
443 		reg = <0x01>;
444 		aspeed,fan-tach-ch = /bits/ 8 <0x05>;
445 	};
446 
447 	fan@6 {
448 		reg = <0x02>;
449 		aspeed,fan-tach-ch = /bits/ 8 <0x06>;
450 	};
451 
452 	fan@7 {
453 		reg = <0x03>;
454 		aspeed,fan-tach-ch = /bits/ 8 <0x07>;
455 	};
456 };
457 
458 &i2c1mux {
459 	i2c@0 {
460 		reg = <0>;
461 		#address-cells = <1>;
462 		#size-cells = <0>;
463 
464 		/* Memory Riser 1 FRU */
465 		eeprom@50 {
466 			compatible = "atmel,24c02";
467 			reg = <0x50>;
468 		};
469 
470 		/* Memory Riser 2 FRU */
471 		eeprom@51 {
472 			compatible = "atmel,24c02";
473 			reg = <0x51>;
474 		};
475 
476 		/* Memory Riser 3 FRU */
477 		eeprom@52 {
478 			compatible = "atmel,24c02";
479 			reg = <0x52>;
480 		};
481 
482 		/* Memory Riser 4 FRU */
483 		eeprom@53 {
484 			compatible = "atmel,24c02";
485 			reg = <0x53>;
486 		};
487 	};
488 
489 	i2c@1 {
490 		reg = <1>;
491 		#address-cells = <1>;
492 		#size-cells = <0>;
493 
494 		/* Memory Riser 5 FRU */
495 		eeprom@50 {
496 			compatible = "atmel,24c02";
497 			reg = <0x50>;
498 		};
499 
500 		/* Memory Riser 6 FRU */
501 		eeprom@51 {
502 			compatible = "atmel,24c02";
503 			reg = <0x51>;
504 		};
505 
506 		/* Memory Riser 7 FRU */
507 		eeprom@52 {
508 			compatible = "atmel,24c02";
509 			reg = <0x52>;
510 		};
511 
512 		/* Memory Riser 8 FRU */
513 		eeprom@53 {
514 			compatible = "atmel,24c02";
515 			reg = <0x53>;
516 		};
517 	};
518 };
519