1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 * Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #ifndef _OCELOT_VCAP_H_ 7 #define _OCELOT_VCAP_H_ 8 9 #include <soc/mscc/ocelot.h> 10 11 /* Cookie definitions for private VCAP filters installed by the driver. 12 * Must be unique per VCAP block. 13 */ 14 #define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream) ((upstream) << 16 | (port)) 15 #define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port) 16 #define OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port) ((ocelot)->num_phys_ports + (port)) 17 #define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port) 18 #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port)) 19 #define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2) 20 #define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1) 21 #define OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 2) 22 #define OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 3) 23 #define OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 4) 24 #define OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 5) 25 26 /* ================================================================= 27 * VCAP Common 28 * ================================================================= 29 */ 30 31 enum { 32 VCAP_ES0, 33 VCAP_IS1, 34 VCAP_IS2, 35 __VCAP_COUNT, 36 }; 37 38 #define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT 39 40 struct vcap_props { 41 u16 tg_width; /* Type-group width (in bits) */ 42 u16 sw_count; /* Sub word count */ 43 u16 entry_count; /* Entry count */ 44 u16 entry_words; /* Number of entry words */ 45 u16 entry_width; /* Entry width (in bits) */ 46 u16 action_count; /* Action count */ 47 u16 action_words; /* Number of action words */ 48 u16 action_width; /* Action width (in bits) */ 49 u16 action_type_width; /* Action type width (in bits) */ 50 struct { 51 u16 width; /* Action type width (in bits) */ 52 u16 count; /* Action type sub word count */ 53 } action_table[2]; 54 u16 counter_words; /* Number of counter words */ 55 u16 counter_width; /* Counter width (in bits) */ 56 57 enum ocelot_target target; 58 59 const struct vcap_field *keys; 60 const struct vcap_field *actions; 61 }; 62 63 /* VCAP Type-Group values */ 64 #define VCAP_TG_NONE 0 /* Entry is invalid */ 65 #define VCAP_TG_FULL 1 /* Full entry */ 66 #define VCAP_TG_HALF 2 /* Half entry */ 67 #define VCAP_TG_QUARTER 3 /* Quarter entry */ 68 69 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22)) 70 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22) 71 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22) 72 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 73 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 74 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 75 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3)) 76 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3) 77 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3) 78 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2) 79 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1) 80 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 81 82 #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16)) 83 #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16) 84 #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16) 85 #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0)) 86 #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0) 87 88 #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4 89 90 #define VCAP_CACHE_MASK_DAT_RSZ 0x4 91 92 #define VCAP_CACHE_ACTION_DAT_RSZ 0x4 93 94 #define VCAP_CACHE_CNT_DAT_RSZ 0x4 95 96 #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 97 98 #define TCAM_BIST_CTRL_TCAM_BIST BIT(1) 99 #define TCAM_BIST_CTRL_TCAM_INIT BIT(0) 100 101 #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8) 102 #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7) 103 #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6) 104 #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0)) 105 #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0) 106 107 #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15) 108 #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14) 109 #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13) 110 #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12) 111 #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11) 112 #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10) 113 #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9) 114 #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8) 115 #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7) 116 #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6) 117 #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5) 118 #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4) 119 #define TCAM_BIST_STAT_BIST_RUN BIT(3) 120 #define TCAM_BIST_STAT_BIST_ERR BIT(2) 121 #define TCAM_BIST_STAT_BIST_BUSY BIT(1) 122 #define TCAM_BIST_STAT_TCAM_RDY BIT(0) 123 124 /* ================================================================= 125 * VCAP IS2 126 * ================================================================= 127 */ 128 129 /* IS2 half key types */ 130 #define IS2_TYPE_ETYPE 0 131 #define IS2_TYPE_LLC 1 132 #define IS2_TYPE_SNAP 2 133 #define IS2_TYPE_ARP 3 134 #define IS2_TYPE_IP_UDP_TCP 4 135 #define IS2_TYPE_IP_OTHER 5 136 #define IS2_TYPE_IPV6 6 137 #define IS2_TYPE_OAM 7 138 #define IS2_TYPE_SMAC_SIP6 8 139 #define IS2_TYPE_ANY 100 /* Pseudo type */ 140 141 /* IS2 half key type mask for matching any IP */ 142 #define IS2_TYPE_MASK_IP_ANY 0xe 143 144 enum { 145 IS2_ACTION_TYPE_NORMAL, 146 IS2_ACTION_TYPE_SMAC_SIP, 147 IS2_ACTION_TYPE_MAX, 148 }; 149 150 /* IS2 MASK_MODE values */ 151 #define IS2_ACT_MASK_MODE_NONE 0 152 #define IS2_ACT_MASK_MODE_FILTER 1 153 #define IS2_ACT_MASK_MODE_POLICY 2 154 #define IS2_ACT_MASK_MODE_REDIR 3 155 156 /* IS2 REW_OP values */ 157 #define IS2_ACT_REW_OP_NONE 0 158 #define IS2_ACT_REW_OP_PTP_ONE 2 159 #define IS2_ACT_REW_OP_PTP_TWO 3 160 #define IS2_ACT_REW_OP_SPECIAL 8 161 #define IS2_ACT_REW_OP_PTP_ORG 9 162 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3)) 163 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3)) 164 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5)) 165 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7) 166 167 #define VCAP_PORT_WIDTH 4 168 169 /* IS2 quarter key - SMAC_SIP4 */ 170 #define IS2_QKO_IGR_PORT 0 171 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH 172 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT) 173 #define IS2_QKL_L2_SMAC 48 174 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC) 175 #define IS2_QKL_L3_IP4_SIP 32 176 177 enum vcap_is2_half_key_field { 178 /* Common */ 179 VCAP_IS2_TYPE, 180 VCAP_IS2_HK_FIRST, 181 VCAP_IS2_HK_PAG, 182 VCAP_IS2_HK_RSV1, 183 VCAP_IS2_HK_IGR_PORT_MASK, 184 VCAP_IS2_HK_RSV2, 185 VCAP_IS2_HK_HOST_MATCH, 186 VCAP_IS2_HK_L2_MC, 187 VCAP_IS2_HK_L2_BC, 188 VCAP_IS2_HK_VLAN_TAGGED, 189 VCAP_IS2_HK_VID, 190 VCAP_IS2_HK_DEI, 191 VCAP_IS2_HK_PCP, 192 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 193 VCAP_IS2_HK_L2_DMAC, 194 VCAP_IS2_HK_L2_SMAC, 195 /* MAC_ETYPE (TYPE=000) */ 196 VCAP_IS2_HK_MAC_ETYPE_ETYPE, 197 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 198 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 199 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 200 /* MAC_LLC (TYPE=001) */ 201 VCAP_IS2_HK_MAC_LLC_DMAC, 202 VCAP_IS2_HK_MAC_LLC_SMAC, 203 VCAP_IS2_HK_MAC_LLC_L2_LLC, 204 /* MAC_SNAP (TYPE=010) */ 205 VCAP_IS2_HK_MAC_SNAP_SMAC, 206 VCAP_IS2_HK_MAC_SNAP_DMAC, 207 VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 208 /* MAC_ARP (TYPE=011) */ 209 VCAP_IS2_HK_MAC_ARP_SMAC, 210 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 211 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 212 VCAP_IS2_HK_MAC_ARP_LEN_OK, 213 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 214 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 215 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 216 VCAP_IS2_HK_MAC_ARP_OPCODE, 217 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 218 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 219 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 220 /* IP4_TCP_UDP / IP4_OTHER common */ 221 VCAP_IS2_HK_IP4, 222 VCAP_IS2_HK_L3_FRAGMENT, 223 VCAP_IS2_HK_L3_FRAG_OFS_GT0, 224 VCAP_IS2_HK_L3_OPTIONS, 225 VCAP_IS2_HK_IP4_L3_TTL_GT0, 226 VCAP_IS2_HK_L3_TOS, 227 VCAP_IS2_HK_L3_IP4_DIP, 228 VCAP_IS2_HK_L3_IP4_SIP, 229 VCAP_IS2_HK_DIP_EQ_SIP, 230 /* IP4_TCP_UDP (TYPE=100) */ 231 VCAP_IS2_HK_TCP, 232 VCAP_IS2_HK_L4_SPORT, 233 VCAP_IS2_HK_L4_DPORT, 234 VCAP_IS2_HK_L4_RNG, 235 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 236 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 237 VCAP_IS2_HK_L4_URG, 238 VCAP_IS2_HK_L4_ACK, 239 VCAP_IS2_HK_L4_PSH, 240 VCAP_IS2_HK_L4_RST, 241 VCAP_IS2_HK_L4_SYN, 242 VCAP_IS2_HK_L4_FIN, 243 VCAP_IS2_HK_L4_1588_DOM, 244 VCAP_IS2_HK_L4_1588_VER, 245 /* IP4_OTHER (TYPE=101) */ 246 VCAP_IS2_HK_IP4_L3_PROTO, 247 VCAP_IS2_HK_L3_PAYLOAD, 248 /* IP6_STD (TYPE=110) */ 249 VCAP_IS2_HK_IP6_L3_TTL_GT0, 250 VCAP_IS2_HK_IP6_L3_PROTO, 251 VCAP_IS2_HK_L3_IP6_SIP, 252 /* OAM (TYPE=111) */ 253 VCAP_IS2_HK_OAM_MEL_FLAGS, 254 VCAP_IS2_HK_OAM_VER, 255 VCAP_IS2_HK_OAM_OPCODE, 256 VCAP_IS2_HK_OAM_FLAGS, 257 VCAP_IS2_HK_OAM_MEPID, 258 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0, 259 VCAP_IS2_HK_OAM_IS_Y1731, 260 }; 261 262 struct vcap_field { 263 int offset; 264 int length; 265 }; 266 267 enum vcap_is2_action_field { 268 VCAP_IS2_ACT_HIT_ME_ONCE, 269 VCAP_IS2_ACT_CPU_COPY_ENA, 270 VCAP_IS2_ACT_CPU_QU_NUM, 271 VCAP_IS2_ACT_MASK_MODE, 272 VCAP_IS2_ACT_MIRROR_ENA, 273 VCAP_IS2_ACT_LRN_DIS, 274 VCAP_IS2_ACT_POLICE_ENA, 275 VCAP_IS2_ACT_POLICE_IDX, 276 VCAP_IS2_ACT_POLICE_VCAP_ONLY, 277 VCAP_IS2_ACT_PORT_MASK, 278 VCAP_IS2_ACT_REW_OP, 279 VCAP_IS2_ACT_SMAC_REPLACE_ENA, 280 VCAP_IS2_ACT_RSV, 281 VCAP_IS2_ACT_ACL_ID, 282 VCAP_IS2_ACT_HIT_CNT, 283 }; 284 285 /* ================================================================= 286 * VCAP IS1 287 * ================================================================= 288 */ 289 290 /* IS1 half key types */ 291 #define IS1_TYPE_S1_NORMAL 0 292 #define IS1_TYPE_S1_5TUPLE_IP4 1 293 294 /* IS1 full key types */ 295 #define IS1_TYPE_S1_NORMAL_IP6 0 296 #define IS1_TYPE_S1_7TUPLE 1 297 #define IS2_TYPE_S1_5TUPLE_IP6 2 298 299 enum { 300 IS1_ACTION_TYPE_NORMAL, 301 IS1_ACTION_TYPE_MAX, 302 }; 303 304 enum vcap_is1_half_key_field { 305 VCAP_IS1_HK_TYPE, 306 VCAP_IS1_HK_LOOKUP, 307 VCAP_IS1_HK_IGR_PORT_MASK, 308 VCAP_IS1_HK_RSV, 309 VCAP_IS1_HK_OAM_Y1731, 310 VCAP_IS1_HK_L2_MC, 311 VCAP_IS1_HK_L2_BC, 312 VCAP_IS1_HK_IP_MC, 313 VCAP_IS1_HK_VLAN_TAGGED, 314 VCAP_IS1_HK_VLAN_DBL_TAGGED, 315 VCAP_IS1_HK_TPID, 316 VCAP_IS1_HK_VID, 317 VCAP_IS1_HK_DEI, 318 VCAP_IS1_HK_PCP, 319 /* Specific Fields for IS1 Half Key S1_NORMAL */ 320 VCAP_IS1_HK_L2_SMAC, 321 VCAP_IS1_HK_ETYPE_LEN, 322 VCAP_IS1_HK_ETYPE, 323 VCAP_IS1_HK_IP_SNAP, 324 VCAP_IS1_HK_IP4, 325 VCAP_IS1_HK_L3_FRAGMENT, 326 VCAP_IS1_HK_L3_FRAG_OFS_GT0, 327 VCAP_IS1_HK_L3_OPTIONS, 328 VCAP_IS1_HK_L3_DSCP, 329 VCAP_IS1_HK_L3_IP4_SIP, 330 VCAP_IS1_HK_TCP_UDP, 331 VCAP_IS1_HK_TCP, 332 VCAP_IS1_HK_L4_SPORT, 333 VCAP_IS1_HK_L4_RNG, 334 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 335 VCAP_IS1_HK_IP4_INNER_TPID, 336 VCAP_IS1_HK_IP4_INNER_VID, 337 VCAP_IS1_HK_IP4_INNER_DEI, 338 VCAP_IS1_HK_IP4_INNER_PCP, 339 VCAP_IS1_HK_IP4_IP4, 340 VCAP_IS1_HK_IP4_L3_FRAGMENT, 341 VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0, 342 VCAP_IS1_HK_IP4_L3_OPTIONS, 343 VCAP_IS1_HK_IP4_L3_DSCP, 344 VCAP_IS1_HK_IP4_L3_IP4_DIP, 345 VCAP_IS1_HK_IP4_L3_IP4_SIP, 346 VCAP_IS1_HK_IP4_L3_PROTO, 347 VCAP_IS1_HK_IP4_TCP_UDP, 348 VCAP_IS1_HK_IP4_TCP, 349 VCAP_IS1_HK_IP4_L4_RNG, 350 VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE, 351 }; 352 353 enum vcap_is1_action_field { 354 VCAP_IS1_ACT_DSCP_ENA, 355 VCAP_IS1_ACT_DSCP_VAL, 356 VCAP_IS1_ACT_QOS_ENA, 357 VCAP_IS1_ACT_QOS_VAL, 358 VCAP_IS1_ACT_DP_ENA, 359 VCAP_IS1_ACT_DP_VAL, 360 VCAP_IS1_ACT_PAG_OVERRIDE_MASK, 361 VCAP_IS1_ACT_PAG_VAL, 362 VCAP_IS1_ACT_RSV, 363 VCAP_IS1_ACT_VID_REPLACE_ENA, 364 VCAP_IS1_ACT_VID_ADD_VAL, 365 VCAP_IS1_ACT_FID_SEL, 366 VCAP_IS1_ACT_FID_VAL, 367 VCAP_IS1_ACT_PCP_DEI_ENA, 368 VCAP_IS1_ACT_PCP_VAL, 369 VCAP_IS1_ACT_DEI_VAL, 370 VCAP_IS1_ACT_VLAN_POP_CNT_ENA, 371 VCAP_IS1_ACT_VLAN_POP_CNT, 372 VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA, 373 VCAP_IS1_ACT_HIT_STICKY, 374 }; 375 376 /* ================================================================= 377 * VCAP ES0 378 * ================================================================= 379 */ 380 381 enum { 382 ES0_ACTION_TYPE_NORMAL, 383 ES0_ACTION_TYPE_MAX, 384 }; 385 386 enum vcap_es0_key_field { 387 VCAP_ES0_EGR_PORT, 388 VCAP_ES0_IGR_PORT, 389 VCAP_ES0_RSV, 390 VCAP_ES0_L2_MC, 391 VCAP_ES0_L2_BC, 392 VCAP_ES0_VID, 393 VCAP_ES0_DP, 394 VCAP_ES0_PCP, 395 }; 396 397 enum vcap_es0_action_field { 398 VCAP_ES0_ACT_PUSH_OUTER_TAG, 399 VCAP_ES0_ACT_PUSH_INNER_TAG, 400 VCAP_ES0_ACT_TAG_A_TPID_SEL, 401 VCAP_ES0_ACT_TAG_A_VID_SEL, 402 VCAP_ES0_ACT_TAG_A_PCP_SEL, 403 VCAP_ES0_ACT_TAG_A_DEI_SEL, 404 VCAP_ES0_ACT_TAG_B_TPID_SEL, 405 VCAP_ES0_ACT_TAG_B_VID_SEL, 406 VCAP_ES0_ACT_TAG_B_PCP_SEL, 407 VCAP_ES0_ACT_TAG_B_DEI_SEL, 408 VCAP_ES0_ACT_VID_A_VAL, 409 VCAP_ES0_ACT_PCP_A_VAL, 410 VCAP_ES0_ACT_DEI_A_VAL, 411 VCAP_ES0_ACT_VID_B_VAL, 412 VCAP_ES0_ACT_PCP_B_VAL, 413 VCAP_ES0_ACT_DEI_B_VAL, 414 VCAP_ES0_ACT_RSV, 415 VCAP_ES0_ACT_HIT_STICKY, 416 }; 417 418 struct ocelot_ipv4 { 419 u8 addr[4]; 420 }; 421 422 enum ocelot_vcap_bit { 423 OCELOT_VCAP_BIT_ANY, 424 OCELOT_VCAP_BIT_0, 425 OCELOT_VCAP_BIT_1 426 }; 427 428 struct ocelot_vcap_u8 { 429 u8 value[1]; 430 u8 mask[1]; 431 }; 432 433 struct ocelot_vcap_u16 { 434 u8 value[2]; 435 u8 mask[2]; 436 }; 437 438 struct ocelot_vcap_u24 { 439 u8 value[3]; 440 u8 mask[3]; 441 }; 442 443 struct ocelot_vcap_u32 { 444 u8 value[4]; 445 u8 mask[4]; 446 }; 447 448 struct ocelot_vcap_u40 { 449 u8 value[5]; 450 u8 mask[5]; 451 }; 452 453 struct ocelot_vcap_u48 { 454 u8 value[6]; 455 u8 mask[6]; 456 }; 457 458 struct ocelot_vcap_u64 { 459 u8 value[8]; 460 u8 mask[8]; 461 }; 462 463 struct ocelot_vcap_u128 { 464 u8 value[16]; 465 u8 mask[16]; 466 }; 467 468 struct ocelot_vcap_vid { 469 u16 value; 470 u16 mask; 471 }; 472 473 struct ocelot_vcap_ipv4 { 474 struct ocelot_ipv4 value; 475 struct ocelot_ipv4 mask; 476 }; 477 478 struct ocelot_vcap_udp_tcp { 479 u16 value; 480 u16 mask; 481 }; 482 483 struct ocelot_vcap_port { 484 u8 value; 485 u8 mask; 486 }; 487 488 enum ocelot_vcap_key_type { 489 OCELOT_VCAP_KEY_ANY, 490 OCELOT_VCAP_KEY_ETYPE, 491 OCELOT_VCAP_KEY_LLC, 492 OCELOT_VCAP_KEY_SNAP, 493 OCELOT_VCAP_KEY_ARP, 494 OCELOT_VCAP_KEY_IPV4, 495 OCELOT_VCAP_KEY_IPV6 496 }; 497 498 struct ocelot_vcap_key_vlan { 499 struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */ 500 struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */ 501 enum ocelot_vcap_bit dei; /* DEI */ 502 enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */ 503 enum ocelot_vcap_bit tpid; 504 }; 505 506 struct ocelot_vcap_key_etype { 507 struct ocelot_vcap_u48 dmac; 508 struct ocelot_vcap_u48 smac; 509 struct ocelot_vcap_u16 etype; 510 struct ocelot_vcap_u16 data; /* MAC data */ 511 }; 512 513 struct ocelot_vcap_key_llc { 514 struct ocelot_vcap_u48 dmac; 515 struct ocelot_vcap_u48 smac; 516 517 /* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */ 518 struct ocelot_vcap_u32 llc; 519 }; 520 521 struct ocelot_vcap_key_snap { 522 struct ocelot_vcap_u48 dmac; 523 struct ocelot_vcap_u48 smac; 524 525 /* SNAP header: Organization Code at byte 0, Type at byte 3 */ 526 struct ocelot_vcap_u40 snap; 527 }; 528 529 struct ocelot_vcap_key_arp { 530 struct ocelot_vcap_u48 smac; 531 enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */ 532 enum ocelot_vcap_bit req; /* Opcode request/reply */ 533 enum ocelot_vcap_bit unknown; /* Opcode unknown */ 534 enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */ 535 enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */ 536 537 /**< Protocol addr. length 4, hardware length 6 */ 538 enum ocelot_vcap_bit length; 539 540 enum ocelot_vcap_bit ip; /* Protocol address type IP */ 541 enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */ 542 struct ocelot_vcap_ipv4 sip; /* Sender IP address */ 543 struct ocelot_vcap_ipv4 dip; /* Target IP address */ 544 }; 545 546 struct ocelot_vcap_key_ipv4 { 547 enum ocelot_vcap_bit ttl; /* TTL zero */ 548 enum ocelot_vcap_bit fragment; /* Fragment */ 549 enum ocelot_vcap_bit options; /* Header options */ 550 struct ocelot_vcap_u8 ds; 551 struct ocelot_vcap_u8 proto; /* Protocol */ 552 struct ocelot_vcap_ipv4 sip; /* Source IP address */ 553 struct ocelot_vcap_ipv4 dip; /* Destination IP address */ 554 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 555 struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */ 556 struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */ 557 enum ocelot_vcap_bit tcp_fin; 558 enum ocelot_vcap_bit tcp_syn; 559 enum ocelot_vcap_bit tcp_rst; 560 enum ocelot_vcap_bit tcp_psh; 561 enum ocelot_vcap_bit tcp_ack; 562 enum ocelot_vcap_bit tcp_urg; 563 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 564 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 565 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 566 }; 567 568 struct ocelot_vcap_key_ipv6 { 569 struct ocelot_vcap_u8 proto; /* IPv6 protocol */ 570 struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */ 571 struct ocelot_vcap_u128 dip; /* IPv6 destination (byte 0-7 ignored) */ 572 enum ocelot_vcap_bit ttl; /* TTL zero */ 573 struct ocelot_vcap_u8 ds; 574 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */ 575 struct ocelot_vcap_udp_tcp sport; 576 struct ocelot_vcap_udp_tcp dport; 577 enum ocelot_vcap_bit tcp_fin; 578 enum ocelot_vcap_bit tcp_syn; 579 enum ocelot_vcap_bit tcp_rst; 580 enum ocelot_vcap_bit tcp_psh; 581 enum ocelot_vcap_bit tcp_ack; 582 enum ocelot_vcap_bit tcp_urg; 583 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */ 584 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */ 585 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */ 586 }; 587 588 enum ocelot_mask_mode { 589 OCELOT_MASK_MODE_NONE, 590 OCELOT_MASK_MODE_PERMIT_DENY, 591 OCELOT_MASK_MODE_POLICY, 592 OCELOT_MASK_MODE_REDIRECT, 593 }; 594 595 enum ocelot_es0_vid_sel { 596 OCELOT_ES0_VID_PLUS_CLASSIFIED_VID = 0, 597 OCELOT_ES0_VID = 1, 598 }; 599 600 enum ocelot_es0_pcp_sel { 601 OCELOT_CLASSIFIED_PCP = 0, 602 OCELOT_ES0_PCP = 1, 603 }; 604 605 enum ocelot_es0_tag { 606 OCELOT_NO_ES0_TAG, 607 OCELOT_ES0_TAG, 608 OCELOT_FORCE_PORT_TAG, 609 OCELOT_FORCE_UNTAG, 610 }; 611 612 enum ocelot_tag_tpid_sel { 613 OCELOT_TAG_TPID_SEL_8021Q, 614 OCELOT_TAG_TPID_SEL_8021AD, 615 }; 616 617 struct ocelot_vcap_action { 618 union { 619 /* VCAP ES0 */ 620 struct { 621 enum ocelot_es0_tag push_outer_tag; 622 enum ocelot_es0_tag push_inner_tag; 623 enum ocelot_tag_tpid_sel tag_a_tpid_sel; 624 int tag_a_vid_sel; 625 int tag_a_pcp_sel; 626 u16 vid_a_val; 627 u8 pcp_a_val; 628 u8 dei_a_val; 629 enum ocelot_tag_tpid_sel tag_b_tpid_sel; 630 int tag_b_vid_sel; 631 int tag_b_pcp_sel; 632 u16 vid_b_val; 633 u8 pcp_b_val; 634 u8 dei_b_val; 635 }; 636 637 /* VCAP IS1 */ 638 struct { 639 bool vid_replace_ena; 640 u16 vid; 641 bool vlan_pop_cnt_ena; 642 int vlan_pop_cnt; 643 bool pcp_dei_ena; 644 u8 pcp; 645 u8 dei; 646 bool qos_ena; 647 u8 qos_val; 648 u8 pag_override_mask; 649 u8 pag_val; 650 }; 651 652 /* VCAP IS2 */ 653 struct { 654 bool cpu_copy_ena; 655 u8 cpu_qu_num; 656 enum ocelot_mask_mode mask_mode; 657 unsigned long port_mask; 658 bool police_ena; 659 bool mirror_ena; 660 struct ocelot_policer pol; 661 u32 pol_ix; 662 }; 663 }; 664 }; 665 666 struct ocelot_vcap_stats { 667 u64 bytes; 668 u64 pkts; 669 u64 used; 670 }; 671 672 enum ocelot_vcap_filter_type { 673 OCELOT_VCAP_FILTER_DUMMY, 674 OCELOT_VCAP_FILTER_PAG, 675 OCELOT_VCAP_FILTER_OFFLOAD, 676 OCELOT_PSFP_FILTER_OFFLOAD, 677 }; 678 679 struct ocelot_vcap_id { 680 unsigned long cookie; 681 bool tc_offload; 682 }; 683 684 struct ocelot_vcap_filter { 685 struct list_head list; 686 687 enum ocelot_vcap_filter_type type; 688 int block_id; 689 int goto_target; 690 int lookup; 691 u8 pag; 692 u16 prio; 693 struct ocelot_vcap_id id; 694 695 struct ocelot_vcap_action action; 696 struct ocelot_vcap_stats stats; 697 /* For VCAP IS1 and IS2 */ 698 bool take_ts; 699 bool is_trap; 700 unsigned long ingress_port_mask; 701 /* For VCAP ES0 */ 702 struct ocelot_vcap_port ingress_port; 703 /* For VCAP IS2 mirrors and ES0 */ 704 struct ocelot_vcap_port egress_port; 705 706 enum ocelot_vcap_bit dmac_mc; 707 enum ocelot_vcap_bit dmac_bc; 708 struct ocelot_vcap_key_vlan vlan; 709 710 enum ocelot_vcap_key_type key_type; 711 union { 712 /* OCELOT_VCAP_KEY_ANY: No specific fields */ 713 struct ocelot_vcap_key_etype etype; 714 struct ocelot_vcap_key_llc llc; 715 struct ocelot_vcap_key_snap snap; 716 struct ocelot_vcap_key_arp arp; 717 struct ocelot_vcap_key_ipv4 ipv4; 718 struct ocelot_vcap_key_ipv6 ipv6; 719 } key; 720 }; 721 722 int ocelot_vcap_filter_add(struct ocelot *ocelot, 723 struct ocelot_vcap_filter *rule, 724 struct netlink_ext_ack *extack); 725 int ocelot_vcap_filter_del(struct ocelot *ocelot, 726 struct ocelot_vcap_filter *rule); 727 int ocelot_vcap_filter_replace(struct ocelot *ocelot, 728 struct ocelot_vcap_filter *filter); 729 struct ocelot_vcap_filter * 730 ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, 731 unsigned long cookie, bool tc_offload); 732 733 #endif /* _OCELOT_VCAP_H_ */ 734