1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PCI Endpoint *Controller* (EPC) header file 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #ifndef __LINUX_PCI_EPC_H 10 #define __LINUX_PCI_EPC_H 11 12 #include <linux/pci-epf.h> 13 14 struct pci_epc; 15 16 enum pci_epc_interface_type { 17 UNKNOWN_INTERFACE = -1, 18 PRIMARY_INTERFACE, 19 SECONDARY_INTERFACE, 20 }; 21 22 static inline const char * pci_epc_interface_string(enum pci_epc_interface_type type)23 pci_epc_interface_string(enum pci_epc_interface_type type) 24 { 25 switch (type) { 26 case PRIMARY_INTERFACE: 27 return "primary"; 28 case SECONDARY_INTERFACE: 29 return "secondary"; 30 default: 31 return "UNKNOWN interface"; 32 } 33 } 34 35 /** 36 * struct pci_epc_ops - set of function pointers for performing EPC operations 37 * @write_header: ops to populate configuration space header 38 * @set_bar: ops to configure the BAR 39 * @clear_bar: ops to reset the BAR 40 * @map_addr: ops to map CPU address to PCI address 41 * @unmap_addr: ops to unmap CPU address and PCI address 42 * @set_msi: ops to set the requested number of MSI interrupts in the MSI 43 * capability register 44 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from 45 * the MSI capability register 46 * @set_msix: ops to set the requested number of MSI-X interrupts in the 47 * MSI-X capability register 48 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC 49 * from the MSI-X capability register 50 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt 51 * @map_msi_irq: ops to map physical address to MSI address and return MSI data 52 * @start: ops to start the PCI link 53 * @stop: ops to stop the PCI link 54 * @get_features: ops to get the features supported by the EPC 55 * @owner: the module owner containing the ops 56 */ 57 struct pci_epc_ops { 58 int (*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 59 struct pci_epf_header *hdr); 60 int (*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 61 struct pci_epf_bar *epf_bar); 62 void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 63 struct pci_epf_bar *epf_bar); 64 int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 65 phys_addr_t addr, u64 pci_addr, size_t size); 66 void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 67 phys_addr_t addr); 68 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 69 u8 interrupts); 70 int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); 71 int (*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 72 u16 interrupts, enum pci_barno, u32 offset); 73 int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); 74 int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 75 unsigned int type, u16 interrupt_num); 76 int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 77 phys_addr_t phys_addr, u8 interrupt_num, 78 u32 entry_size, u32 *msi_data, 79 u32 *msi_addr_offset); 80 int (*start)(struct pci_epc *epc); 81 void (*stop)(struct pci_epc *epc); 82 const struct pci_epc_features* (*get_features)(struct pci_epc *epc, 83 u8 func_no, u8 vfunc_no); 84 struct module *owner; 85 }; 86 87 /** 88 * struct pci_epc_mem_window - address window of the endpoint controller 89 * @phys_base: physical base address of the PCI address window 90 * @size: the size of the PCI address window 91 * @page_size: size of each page 92 */ 93 struct pci_epc_mem_window { 94 phys_addr_t phys_base; 95 size_t size; 96 size_t page_size; 97 }; 98 99 /** 100 * struct pci_epc_mem - address space of the endpoint controller 101 * @window: address window of the endpoint controller 102 * @bitmap: bitmap to manage the PCI address space 103 * @pages: number of bits representing the address region 104 * @lock: mutex to protect bitmap 105 */ 106 struct pci_epc_mem { 107 struct pci_epc_mem_window window; 108 unsigned long *bitmap; 109 int pages; 110 /* mutex to protect against concurrent access for memory allocation*/ 111 struct mutex lock; 112 }; 113 114 /** 115 * struct pci_epc - represents the PCI EPC device 116 * @dev: PCI EPC device 117 * @pci_epf: list of endpoint functions present in this EPC device 118 * @list_lock: Mutex for protecting pci_epf list 119 * @ops: function pointers for performing endpoint operations 120 * @windows: array of address space of the endpoint controller 121 * @mem: first window of the endpoint controller, which corresponds to 122 * default address space of the endpoint controller supporting 123 * single window. 124 * @num_windows: number of windows supported by device 125 * @max_functions: max number of functions that can be configured in this EPC 126 * @max_vfs: Array indicating the maximum number of virtual functions that can 127 * be associated with each physical function 128 * @group: configfs group representing the PCI EPC device 129 * @lock: mutex to protect pci_epc ops 130 * @function_num_map: bitmap to manage physical function number 131 * @domain_nr: PCI domain number of the endpoint controller 132 * @init_complete: flag to indicate whether the EPC initialization is complete 133 * or not 134 */ 135 struct pci_epc { 136 struct device dev; 137 struct list_head pci_epf; 138 struct mutex list_lock; 139 const struct pci_epc_ops *ops; 140 struct pci_epc_mem **windows; 141 struct pci_epc_mem *mem; 142 unsigned int num_windows; 143 u8 max_functions; 144 u8 *max_vfs; 145 struct config_group *group; 146 /* mutex to protect against concurrent access of EP controller */ 147 struct mutex lock; 148 unsigned long function_num_map; 149 int domain_nr; 150 bool init_complete; 151 }; 152 153 /** 154 * enum pci_epc_bar_type - configurability of endpoint BAR 155 * @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC. 156 * @BAR_FIXED: The BAR mask is fixed by the hardware. 157 * @BAR_RESERVED: The BAR should not be touched by an EPF driver. 158 */ 159 enum pci_epc_bar_type { 160 BAR_PROGRAMMABLE = 0, 161 BAR_FIXED, 162 BAR_RESERVED, 163 }; 164 165 /** 166 * struct pci_epc_bar_desc - hardware description for a BAR 167 * @type: the type of the BAR 168 * @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK. 169 * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR 170 * should be configured as 32-bit or 64-bit, the EPF driver must 171 * configure this BAR as 64-bit. Additionally, the BAR succeeding 172 * this BAR must be set to type BAR_RESERVED. 173 * 174 * only_64bit should not be set on a BAR of type BAR_RESERVED. 175 * (If BARx is a 64-bit BAR that an EPF driver is not allowed to 176 * touch, then both BARx and BARx+1 must be set to type 177 * BAR_RESERVED.) 178 */ 179 struct pci_epc_bar_desc { 180 enum pci_epc_bar_type type; 181 u64 fixed_size; 182 bool only_64bit; 183 }; 184 185 /** 186 * struct pci_epc_features - features supported by a EPC device per function 187 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up 188 * @msi_capable: indicate if the endpoint function has MSI capability 189 * @msix_capable: indicate if the endpoint function has MSI-X capability 190 * @bar: array specifying the hardware description for each BAR 191 * @align: alignment size required for BAR buffer allocation 192 */ 193 struct pci_epc_features { 194 unsigned int linkup_notifier : 1; 195 unsigned int msi_capable : 1; 196 unsigned int msix_capable : 1; 197 struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS]; 198 size_t align; 199 }; 200 201 #define to_pci_epc(device) container_of((device), struct pci_epc, dev) 202 203 #ifdef CONFIG_PCI_ENDPOINT 204 205 #define pci_epc_create(dev, ops) \ 206 __pci_epc_create((dev), (ops), THIS_MODULE) 207 #define devm_pci_epc_create(dev, ops) \ 208 __devm_pci_epc_create((dev), (ops), THIS_MODULE) 209 epc_set_drvdata(struct pci_epc * epc,void * data)210 static inline void epc_set_drvdata(struct pci_epc *epc, void *data) 211 { 212 dev_set_drvdata(&epc->dev, data); 213 } 214 epc_get_drvdata(struct pci_epc * epc)215 static inline void *epc_get_drvdata(struct pci_epc *epc) 216 { 217 return dev_get_drvdata(&epc->dev); 218 } 219 220 struct pci_epc * 221 __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 222 struct module *owner); 223 struct pci_epc * 224 __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 225 struct module *owner); 226 void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); 227 void pci_epc_destroy(struct pci_epc *epc); 228 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, 229 enum pci_epc_interface_type type); 230 void pci_epc_linkup(struct pci_epc *epc); 231 void pci_epc_linkdown(struct pci_epc *epc); 232 void pci_epc_init_notify(struct pci_epc *epc); 233 void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf); 234 void pci_epc_deinit_notify(struct pci_epc *epc); 235 void pci_epc_bus_master_enable_notify(struct pci_epc *epc); 236 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, 237 enum pci_epc_interface_type type); 238 int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 239 struct pci_epf_header *hdr); 240 int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 241 struct pci_epf_bar *epf_bar); 242 void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 243 struct pci_epf_bar *epf_bar); 244 int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 245 phys_addr_t phys_addr, 246 u64 pci_addr, size_t size); 247 void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 248 phys_addr_t phys_addr); 249 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 250 u8 interrupts); 251 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no); 252 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 253 u16 interrupts, enum pci_barno, u32 offset); 254 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); 255 int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 256 phys_addr_t phys_addr, u8 interrupt_num, 257 u32 entry_size, u32 *msi_data, u32 *msi_addr_offset); 258 int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, 259 unsigned int type, u16 interrupt_num); 260 int pci_epc_start(struct pci_epc *epc); 261 void pci_epc_stop(struct pci_epc *epc); 262 const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, 263 u8 func_no, u8 vfunc_no); 264 enum pci_barno 265 pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); 266 enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features 267 *epc_features, enum pci_barno bar); 268 struct pci_epc *pci_epc_get(const char *epc_name); 269 void pci_epc_put(struct pci_epc *epc); 270 271 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base, 272 size_t size, size_t page_size); 273 int pci_epc_multi_mem_init(struct pci_epc *epc, 274 struct pci_epc_mem_window *window, 275 unsigned int num_windows); 276 void pci_epc_mem_exit(struct pci_epc *epc); 277 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, 278 phys_addr_t *phys_addr, size_t size); 279 void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, 280 void __iomem *virt_addr, size_t size); 281 282 #else pci_epc_init_notify(struct pci_epc * epc)283 static inline void pci_epc_init_notify(struct pci_epc *epc) 284 { 285 } 286 pci_epc_deinit_notify(struct pci_epc * epc)287 static inline void pci_epc_deinit_notify(struct pci_epc *epc) 288 { 289 } 290 #endif /* CONFIG_PCI_ENDPOINT */ 291 #endif /* __LINUX_PCI_EPC_H */ 292