1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * core.c - DesignWare HS OTG Controller common routines
4  *
5  * Copyright (C) 2004-2013 Synopsys, Inc.
6  */
7 
8 /*
9  * The Core code provides basic services for accessing and managing the
10  * DWC_otg hardware. These services are used by both the Host Controller
11  * Driver and the Peripheral Controller Driver.
12  */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22 #include <linux/usb.h>
23 
24 #include <linux/usb/hcd.h>
25 #include <linux/usb/ch11.h>
26 
27 #include "core.h"
28 #include "hcd.h"
29 
30 /**
31  * dwc2_backup_global_registers() - Backup global controller registers.
32  * When suspending usb bus, registers needs to be backuped
33  * if controller power is disabled once suspended.
34  *
35  * @hsotg: Programming view of the DWC_otg controller
36  */
dwc2_backup_global_registers(struct dwc2_hsotg * hsotg)37 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
38 {
39 	struct dwc2_gregs_backup *gr;
40 
41 	dev_dbg(hsotg->dev, "%s\n", __func__);
42 
43 	/* Backup global regs */
44 	gr = &hsotg->gr_backup;
45 
46 	gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
47 	gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
48 	gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
49 	gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
50 	gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
51 	gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
52 	gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
53 	gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
54 	gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
55 	gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
56 	gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
57 
58 	gr->valid = true;
59 	return 0;
60 }
61 
62 /**
63  * dwc2_restore_global_registers() - Restore controller global registers.
64  * When resuming usb bus, device registers needs to be restored
65  * if controller power were disabled.
66  *
67  * @hsotg: Programming view of the DWC_otg controller
68  */
dwc2_restore_global_registers(struct dwc2_hsotg * hsotg)69 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
70 {
71 	struct dwc2_gregs_backup *gr;
72 
73 	dev_dbg(hsotg->dev, "%s\n", __func__);
74 
75 	/* Restore global regs */
76 	gr = &hsotg->gr_backup;
77 	if (!gr->valid) {
78 		dev_err(hsotg->dev, "%s: no global registers to restore\n",
79 			__func__);
80 		return -EINVAL;
81 	}
82 	gr->valid = false;
83 
84 	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
85 	dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
86 	dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
87 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
88 	dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
89 	dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
90 	dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
91 	dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
92 	dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
93 	dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
94 	dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
95 	dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
96 
97 	return 0;
98 }
99 
100 /**
101  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
102  *
103  * @hsotg: Programming view of the DWC_otg controller
104  * @rem_wakeup: indicates whether resume is initiated by Reset.
105  * @restore: Controller registers need to be restored
106  */
dwc2_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)107 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
108 				 bool restore)
109 {
110 	struct dwc2_gregs_backup *gr;
111 
112 	gr = &hsotg->gr_backup;
113 
114 	/*
115 	 * Restore host or device regisers with the same mode core enterted
116 	 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
117 	 * value of the "gotgctl" register.
118 	 */
119 	if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
120 		return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
121 							 restore);
122 	else
123 		return dwc2_gadget_exit_partial_power_down(hsotg, restore);
124 }
125 
126 /**
127  * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
128  *
129  * @hsotg: Programming view of the DWC_otg controller
130  */
dwc2_enter_partial_power_down(struct dwc2_hsotg * hsotg)131 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
132 {
133 	if (dwc2_is_host_mode(hsotg))
134 		return dwc2_host_enter_partial_power_down(hsotg);
135 	else
136 		return dwc2_gadget_enter_partial_power_down(hsotg);
137 }
138 
139 /**
140  * dwc2_restore_essential_regs() - Restore essiential regs of core.
141  *
142  * @hsotg: Programming view of the DWC_otg controller
143  * @rmode: Restore mode, enabled in case of remote-wakeup.
144  * @is_host: Host or device mode.
145  */
dwc2_restore_essential_regs(struct dwc2_hsotg * hsotg,int rmode,int is_host)146 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
147 					int is_host)
148 {
149 	u32 pcgcctl;
150 	struct dwc2_gregs_backup *gr;
151 	struct dwc2_dregs_backup *dr;
152 	struct dwc2_hregs_backup *hr;
153 
154 	gr = &hsotg->gr_backup;
155 	dr = &hsotg->dr_backup;
156 	hr = &hsotg->hr_backup;
157 
158 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
159 
160 	/* Load restore values for [31:14] bits */
161 	pcgcctl = (gr->pcgcctl & 0xffffc000);
162 	/* If High Speed */
163 	if (is_host) {
164 		if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
165 			pcgcctl |= BIT(17);
166 	} else {
167 		if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
168 			pcgcctl |= BIT(17);
169 	}
170 	dwc2_writel(hsotg, pcgcctl, PCGCTL);
171 
172 	/* Umnask global Interrupt in GAHBCFG and restore it */
173 	dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
174 
175 	/* Clear all pending interupts */
176 	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
177 
178 	/* Unmask restore done interrupt */
179 	dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
180 
181 	/* Restore GUSBCFG and HCFG/DCFG */
182 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
183 
184 	if (is_host) {
185 		dwc2_writel(hsotg, hr->hcfg, HCFG);
186 		if (rmode)
187 			pcgcctl |= PCGCTL_RESTOREMODE;
188 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
189 		udelay(10);
190 
191 		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
192 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
193 		udelay(10);
194 	} else {
195 		dwc2_writel(hsotg, dr->dcfg, DCFG);
196 		if (!rmode)
197 			pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
198 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
199 		udelay(10);
200 
201 		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
202 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
203 		udelay(10);
204 	}
205 }
206 
207 /**
208  * dwc2_hib_restore_common() - Common part of restore routine.
209  *
210  * @hsotg: Programming view of the DWC_otg controller
211  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
212  * @is_host: Host or device mode.
213  */
dwc2_hib_restore_common(struct dwc2_hsotg * hsotg,int rem_wakeup,int is_host)214 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
215 			     int is_host)
216 {
217 	u32 gpwrdn;
218 
219 	/* Switch-on voltage to the core */
220 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
221 	gpwrdn &= ~GPWRDN_PWRDNSWTCH;
222 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
223 	udelay(10);
224 
225 	/* Reset core */
226 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
227 	gpwrdn &= ~GPWRDN_PWRDNRSTN;
228 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
229 	udelay(10);
230 
231 	/* Enable restore from PMU */
232 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
233 	gpwrdn |= GPWRDN_RESTORE;
234 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
235 	udelay(10);
236 
237 	/* Disable Power Down Clamp */
238 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
239 	gpwrdn &= ~GPWRDN_PWRDNCLMP;
240 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
241 	udelay(50);
242 
243 	if (!is_host && rem_wakeup)
244 		udelay(70);
245 
246 	/* Deassert reset core */
247 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
248 	gpwrdn |= GPWRDN_PWRDNRSTN;
249 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
250 	udelay(10);
251 
252 	/* Reset ULPI latch */
253 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
254 	gpwrdn &= ~GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY;
255 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
256 
257 	/* Disable PMU interrupt */
258 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
259 	gpwrdn &= ~GPWRDN_PMUINTSEL;
260 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
261 	udelay(10);
262 
263 	/* Set Restore Essential Regs bit in PCGCCTL register */
264 	dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
265 
266 	/*
267 	 * Wait For Restore_done Interrupt. This mechanism of polling the
268 	 * interrupt is introduced to avoid any possible race conditions
269 	 */
270 	if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
271 				    20000)) {
272 		dev_dbg(hsotg->dev,
273 			"%s: Restore Done wasn't generated here\n",
274 			__func__);
275 	} else {
276 		dev_dbg(hsotg->dev, "restore done  generated here\n");
277 
278 		/*
279 		 * To avoid restore done interrupt storm after restore is
280 		 * generated clear GINTSTS_RESTOREDONE bit.
281 		 */
282 		dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
283 	}
284 }
285 
286 /**
287  * dwc2_wait_for_mode() - Waits for the controller mode.
288  * @hsotg:	Programming view of the DWC_otg controller.
289  * @host_mode:	If true, waits for host mode, otherwise device mode.
290  */
dwc2_wait_for_mode(struct dwc2_hsotg * hsotg,bool host_mode)291 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
292 			       bool host_mode)
293 {
294 	ktime_t start;
295 	ktime_t end;
296 	unsigned int timeout = 110;
297 
298 	dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
299 		 host_mode ? "host" : "device");
300 
301 	start = ktime_get();
302 
303 	while (1) {
304 		s64 ms;
305 
306 		if (dwc2_is_host_mode(hsotg) == host_mode) {
307 			dev_vdbg(hsotg->dev, "%s mode set\n",
308 				 host_mode ? "Host" : "Device");
309 			break;
310 		}
311 
312 		end = ktime_get();
313 		ms = ktime_to_ms(ktime_sub(end, start));
314 
315 		if (ms >= (s64)timeout) {
316 			dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
317 				 __func__, host_mode ? "host" : "device");
318 			break;
319 		}
320 
321 		usleep_range(1000, 2000);
322 	}
323 }
324 
325 /**
326  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
327  * filter is enabled.
328  *
329  * @hsotg: Programming view of DWC_otg controller
330  */
dwc2_iddig_filter_enabled(struct dwc2_hsotg * hsotg)331 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
332 {
333 	u32 gsnpsid;
334 	u32 ghwcfg4;
335 
336 	if (!dwc2_hw_is_otg(hsotg))
337 		return false;
338 
339 	/* Check if core configuration includes the IDDIG filter. */
340 	ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
341 	if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
342 		return false;
343 
344 	/*
345 	 * Check if the IDDIG debounce filter is bypassed. Available
346 	 * in core version >= 3.10a.
347 	 */
348 	gsnpsid = dwc2_readl(hsotg, GSNPSID);
349 	if (gsnpsid >= DWC2_CORE_REV_3_10a) {
350 		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
351 
352 		if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
353 			return false;
354 	}
355 
356 	return true;
357 }
358 
359 /*
360  * dwc2_enter_hibernation() - Common function to enter hibernation.
361  *
362  * @hsotg: Programming view of the DWC_otg controller
363  * @is_host: True if core is in host mode.
364  *
365  * Return: 0 if successful, negative error code otherwise
366  */
dwc2_enter_hibernation(struct dwc2_hsotg * hsotg,int is_host)367 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
368 {
369 	if (is_host)
370 		return dwc2_host_enter_hibernation(hsotg);
371 	else
372 		return dwc2_gadget_enter_hibernation(hsotg);
373 }
374 
375 /*
376  * dwc2_exit_hibernation() - Common function to exit from hibernation.
377  *
378  * @hsotg: Programming view of the DWC_otg controller
379  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
380  * @reset: Enabled in case of restore with reset.
381  * @is_host: True if core is in host mode.
382  *
383  * Return: 0 if successful, negative error code otherwise
384  */
dwc2_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset,int is_host)385 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
386 			  int reset, int is_host)
387 {
388 	if (is_host)
389 		return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
390 	else
391 		return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
392 }
393 
394 /*
395  * Do core a soft reset of the core.  Be careful with this because it
396  * resets all the internal state machines of the core.
397  */
dwc2_core_reset(struct dwc2_hsotg * hsotg,bool skip_wait)398 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
399 {
400 	u32 greset;
401 	bool wait_for_host_mode = false;
402 
403 	dev_vdbg(hsotg->dev, "%s()\n", __func__);
404 
405 	/*
406 	 * If the current mode is host, either due to the force mode
407 	 * bit being set (which persists after core reset) or the
408 	 * connector id pin, a core soft reset will temporarily reset
409 	 * the mode to device. A delay from the IDDIG debounce filter
410 	 * will occur before going back to host mode.
411 	 *
412 	 * Determine whether we will go back into host mode after a
413 	 * reset and account for this delay after the reset.
414 	 */
415 	if (dwc2_iddig_filter_enabled(hsotg)) {
416 		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
417 		u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
418 
419 		if (!(gotgctl & GOTGCTL_CONID_B) ||
420 		    (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
421 			wait_for_host_mode = true;
422 		}
423 	}
424 
425 	/* Core Soft Reset */
426 	greset = dwc2_readl(hsotg, GRSTCTL);
427 	greset |= GRSTCTL_CSFTRST;
428 	dwc2_writel(hsotg, greset, GRSTCTL);
429 
430 	if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
431 		(DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
432 		if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
433 					      GRSTCTL_CSFTRST, 10000)) {
434 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
435 				 __func__);
436 			return -EBUSY;
437 		}
438 	} else {
439 		if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
440 					    GRSTCTL_CSFTRST_DONE, 10000)) {
441 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
442 				 __func__);
443 			return -EBUSY;
444 		}
445 		greset = dwc2_readl(hsotg, GRSTCTL);
446 		greset &= ~GRSTCTL_CSFTRST;
447 		greset |= GRSTCTL_CSFTRST_DONE;
448 		dwc2_writel(hsotg, greset, GRSTCTL);
449 	}
450 
451 	/*
452 	 * Switching from device mode to host mode by disconnecting
453 	 * device cable core enters and exits form hibernation.
454 	 * However, the fifo map remains not cleared. It results
455 	 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
456 	 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
457 	 * if in host mode we disconnect the micro a to b host
458 	 * cable. Because core reset occurs.
459 	 * To avoid the WARNING, fifo_map should be cleared
460 	 * in dwc2_core_reset() function by taking into account configs.
461 	 * fifo_map must be cleared only if driver is configured in
462 	 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
463 	 * mode.
464 	 */
465 	dwc2_clear_fifo_map(hsotg);
466 
467 	/* Wait for AHB master IDLE state */
468 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
469 		dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
470 			 __func__);
471 		return -EBUSY;
472 	}
473 
474 	if (wait_for_host_mode && !skip_wait)
475 		dwc2_wait_for_mode(hsotg, true);
476 
477 	return 0;
478 }
479 
480 /**
481  * dwc2_force_mode() - Force the mode of the controller.
482  *
483  * Forcing the mode is needed for two cases:
484  *
485  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
486  * controller to stay in a particular mode regardless of ID pin
487  * changes. We do this once during probe.
488  *
489  * 2) During probe we want to read reset values of the hw
490  * configuration registers that are only available in either host or
491  * device mode. We may need to force the mode if the current mode does
492  * not allow us to access the register in the mode that we want.
493  *
494  * In either case it only makes sense to force the mode if the
495  * controller hardware is OTG capable.
496  *
497  * Checks are done in this function to determine whether doing a force
498  * would be valid or not.
499  *
500  * If a force is done, it requires a IDDIG debounce filter delay if
501  * the filter is configured and enabled. We poll the current mode of
502  * the controller to account for this delay.
503  *
504  * @hsotg: Programming view of DWC_otg controller
505  * @host: Host mode flag
506  */
dwc2_force_mode(struct dwc2_hsotg * hsotg,bool host)507 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
508 {
509 	u32 gusbcfg;
510 	u32 set;
511 	u32 clear;
512 
513 	dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
514 
515 	/*
516 	 * Force mode has no effect if the hardware is not OTG.
517 	 */
518 	if (!dwc2_hw_is_otg(hsotg))
519 		return;
520 
521 	/*
522 	 * If dr_mode is either peripheral or host only, there is no
523 	 * need to ever force the mode to the opposite mode.
524 	 */
525 	if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
526 		return;
527 
528 	if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
529 		return;
530 
531 	gusbcfg = dwc2_readl(hsotg, GUSBCFG);
532 
533 	set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
534 	clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
535 
536 	gusbcfg &= ~clear;
537 	gusbcfg |= set;
538 	dwc2_writel(hsotg, gusbcfg, GUSBCFG);
539 
540 	dwc2_wait_for_mode(hsotg, host);
541 	return;
542 }
543 
544 /**
545  * dwc2_clear_force_mode() - Clears the force mode bits.
546  *
547  * After clearing the bits, wait up to 100 ms to account for any
548  * potential IDDIG filter delay. We can't know if we expect this delay
549  * or not because the value of the connector ID status is affected by
550  * the force mode. We only need to call this once during probe if
551  * dr_mode == OTG.
552  *
553  * @hsotg: Programming view of DWC_otg controller
554  */
dwc2_clear_force_mode(struct dwc2_hsotg * hsotg)555 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
556 {
557 	u32 gusbcfg;
558 
559 	if (!dwc2_hw_is_otg(hsotg))
560 		return;
561 
562 	dev_dbg(hsotg->dev, "Clearing force mode bits\n");
563 
564 	gusbcfg = dwc2_readl(hsotg, GUSBCFG);
565 	gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
566 	gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
567 	dwc2_writel(hsotg, gusbcfg, GUSBCFG);
568 
569 	if (dwc2_iddig_filter_enabled(hsotg))
570 		msleep(100);
571 }
572 
573 /*
574  * Sets or clears force mode based on the dr_mode parameter.
575  */
dwc2_force_dr_mode(struct dwc2_hsotg * hsotg)576 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
577 {
578 	switch (hsotg->dr_mode) {
579 	case USB_DR_MODE_HOST:
580 		/*
581 		 * NOTE: This is required for some rockchip soc based
582 		 * platforms on their host-only dwc2.
583 		 */
584 		if (!dwc2_hw_is_otg(hsotg))
585 			msleep(50);
586 
587 		break;
588 	case USB_DR_MODE_PERIPHERAL:
589 		dwc2_force_mode(hsotg, false);
590 		break;
591 	case USB_DR_MODE_OTG:
592 		dwc2_clear_force_mode(hsotg);
593 		break;
594 	default:
595 		dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
596 			 __func__, hsotg->dr_mode);
597 		break;
598 	}
599 }
600 
601 /*
602  * dwc2_enable_acg - enable active clock gating feature
603  */
dwc2_enable_acg(struct dwc2_hsotg * hsotg)604 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
605 {
606 	if (hsotg->params.acg_enable) {
607 		u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
608 
609 		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
610 		pcgcctl1 |= PCGCCTL1_GATEEN;
611 		dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
612 	}
613 }
614 
615 /**
616  * dwc2_dump_host_registers() - Prints the host registers
617  *
618  * @hsotg: Programming view of DWC_otg controller
619  *
620  * NOTE: This function will be removed once the peripheral controller code
621  * is integrated and the driver is stable
622  */
dwc2_dump_host_registers(struct dwc2_hsotg * hsotg)623 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
624 {
625 #ifdef DEBUG
626 	u32 __iomem *addr;
627 	int i;
628 
629 	dev_dbg(hsotg->dev, "Host Global Registers\n");
630 	addr = hsotg->regs + HCFG;
631 	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",
632 		(unsigned long)addr, dwc2_readl(hsotg, HCFG));
633 	addr = hsotg->regs + HFIR;
634 	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",
635 		(unsigned long)addr, dwc2_readl(hsotg, HFIR));
636 	addr = hsotg->regs + HFNUM;
637 	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",
638 		(unsigned long)addr, dwc2_readl(hsotg, HFNUM));
639 	addr = hsotg->regs + HPTXSTS;
640 	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",
641 		(unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
642 	addr = hsotg->regs + HAINT;
643 	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",
644 		(unsigned long)addr, dwc2_readl(hsotg, HAINT));
645 	addr = hsotg->regs + HAINTMSK;
646 	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",
647 		(unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
648 	if (hsotg->params.dma_desc_enable) {
649 		addr = hsotg->regs + HFLBADDR;
650 		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
651 			(unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
652 	}
653 
654 	addr = hsotg->regs + HPRT0;
655 	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",
656 		(unsigned long)addr, dwc2_readl(hsotg, HPRT0));
657 
658 	for (i = 0; i < hsotg->params.host_channels; i++) {
659 		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
660 		addr = hsotg->regs + HCCHAR(i);
661 		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",
662 			(unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
663 		addr = hsotg->regs + HCSPLT(i);
664 		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",
665 			(unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
666 		addr = hsotg->regs + HCINT(i);
667 		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",
668 			(unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
669 		addr = hsotg->regs + HCINTMSK(i);
670 		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",
671 			(unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
672 		addr = hsotg->regs + HCTSIZ(i);
673 		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",
674 			(unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
675 		addr = hsotg->regs + HCDMA(i);
676 		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",
677 			(unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
678 		if (hsotg->params.dma_desc_enable) {
679 			addr = hsotg->regs + HCDMAB(i);
680 			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",
681 				(unsigned long)addr, dwc2_readl(hsotg,
682 								HCDMAB(i)));
683 		}
684 	}
685 #endif
686 }
687 
688 /**
689  * dwc2_dump_global_registers() - Prints the core global registers
690  *
691  * @hsotg: Programming view of DWC_otg controller
692  *
693  * NOTE: This function will be removed once the peripheral controller code
694  * is integrated and the driver is stable
695  */
dwc2_dump_global_registers(struct dwc2_hsotg * hsotg)696 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
697 {
698 #ifdef DEBUG
699 	u32 __iomem *addr;
700 
701 	dev_dbg(hsotg->dev, "Core Global Registers\n");
702 	addr = hsotg->regs + GOTGCTL;
703 	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",
704 		(unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
705 	addr = hsotg->regs + GOTGINT;
706 	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",
707 		(unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
708 	addr = hsotg->regs + GAHBCFG;
709 	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",
710 		(unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
711 	addr = hsotg->regs + GUSBCFG;
712 	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",
713 		(unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
714 	addr = hsotg->regs + GRSTCTL;
715 	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",
716 		(unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
717 	addr = hsotg->regs + GINTSTS;
718 	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",
719 		(unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
720 	addr = hsotg->regs + GINTMSK;
721 	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",
722 		(unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
723 	addr = hsotg->regs + GRXSTSR;
724 	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",
725 		(unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
726 	addr = hsotg->regs + GRXFSIZ;
727 	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",
728 		(unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
729 	addr = hsotg->regs + GNPTXFSIZ;
730 	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",
731 		(unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
732 	addr = hsotg->regs + GNPTXSTS;
733 	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",
734 		(unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
735 	addr = hsotg->regs + GI2CCTL;
736 	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",
737 		(unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
738 	addr = hsotg->regs + GPVNDCTL;
739 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",
740 		(unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
741 	addr = hsotg->regs + GGPIO;
742 	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",
743 		(unsigned long)addr, dwc2_readl(hsotg, GGPIO));
744 	addr = hsotg->regs + GUID;
745 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",
746 		(unsigned long)addr, dwc2_readl(hsotg, GUID));
747 	addr = hsotg->regs + GSNPSID;
748 	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",
749 		(unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
750 	addr = hsotg->regs + GHWCFG1;
751 	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",
752 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
753 	addr = hsotg->regs + GHWCFG2;
754 	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",
755 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
756 	addr = hsotg->regs + GHWCFG3;
757 	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",
758 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
759 	addr = hsotg->regs + GHWCFG4;
760 	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",
761 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
762 	addr = hsotg->regs + GLPMCFG;
763 	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",
764 		(unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
765 	addr = hsotg->regs + GPWRDN;
766 	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",
767 		(unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
768 	addr = hsotg->regs + GDFIFOCFG;
769 	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",
770 		(unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
771 	addr = hsotg->regs + HPTXFSIZ;
772 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",
773 		(unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
774 
775 	addr = hsotg->regs + PCGCTL;
776 	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",
777 		(unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
778 #endif
779 }
780 
781 /**
782  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
783  *
784  * @hsotg: Programming view of DWC_otg controller
785  * @num:   Tx FIFO to flush
786  */
dwc2_flush_tx_fifo(struct dwc2_hsotg * hsotg,const int num)787 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
788 {
789 	u32 greset;
790 
791 	dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
792 
793 	/* Wait for AHB master IDLE state */
794 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
795 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
796 			 __func__);
797 
798 	greset = GRSTCTL_TXFFLSH;
799 	greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
800 	dwc2_writel(hsotg, greset, GRSTCTL);
801 
802 	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
803 		dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
804 			 __func__);
805 
806 	/* Wait for at least 3 PHY Clocks */
807 	udelay(1);
808 }
809 
810 /**
811  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
812  *
813  * @hsotg: Programming view of DWC_otg controller
814  */
dwc2_flush_rx_fifo(struct dwc2_hsotg * hsotg)815 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
816 {
817 	u32 greset;
818 
819 	dev_vdbg(hsotg->dev, "%s()\n", __func__);
820 
821 	/* Wait for AHB master IDLE state */
822 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
823 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
824 			 __func__);
825 
826 	greset = GRSTCTL_RXFFLSH;
827 	dwc2_writel(hsotg, greset, GRSTCTL);
828 
829 	/* Wait for RxFIFO flush done */
830 	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
831 		dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
832 			 __func__);
833 
834 	/* Wait for at least 3 PHY Clocks */
835 	udelay(1);
836 }
837 
dwc2_is_controller_alive(struct dwc2_hsotg * hsotg)838 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
839 {
840 	if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
841 		return false;
842 	else
843 		return true;
844 }
845 
846 /**
847  * dwc2_enable_global_interrupts() - Enables the controller's Global
848  * Interrupt in the AHB Config register
849  *
850  * @hsotg: Programming view of DWC_otg controller
851  */
dwc2_enable_global_interrupts(struct dwc2_hsotg * hsotg)852 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
853 {
854 	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
855 
856 	ahbcfg |= GAHBCFG_GLBL_INTR_EN;
857 	dwc2_writel(hsotg, ahbcfg, GAHBCFG);
858 }
859 
860 /**
861  * dwc2_disable_global_interrupts() - Disables the controller's Global
862  * Interrupt in the AHB Config register
863  *
864  * @hsotg: Programming view of DWC_otg controller
865  */
dwc2_disable_global_interrupts(struct dwc2_hsotg * hsotg)866 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
867 {
868 	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
869 
870 	ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
871 	dwc2_writel(hsotg, ahbcfg, GAHBCFG);
872 }
873 
874 /* Returns the controller's GHWCFG2.OTG_MODE. */
dwc2_op_mode(struct dwc2_hsotg * hsotg)875 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
876 {
877 	u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
878 
879 	return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
880 		GHWCFG2_OP_MODE_SHIFT;
881 }
882 
883 /* Returns true if the controller is capable of DRD. */
dwc2_hw_is_otg(struct dwc2_hsotg * hsotg)884 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
885 {
886 	unsigned int op_mode = dwc2_op_mode(hsotg);
887 
888 	return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
889 		(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
890 		(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
891 }
892 
893 /* Returns true if the controller is host-only. */
dwc2_hw_is_host(struct dwc2_hsotg * hsotg)894 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
895 {
896 	unsigned int op_mode = dwc2_op_mode(hsotg);
897 
898 	return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
899 		(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
900 }
901 
902 /* Returns true if the controller is device-only. */
dwc2_hw_is_device(struct dwc2_hsotg * hsotg)903 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
904 {
905 	unsigned int op_mode = dwc2_op_mode(hsotg);
906 
907 	return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
908 		(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
909 }
910 
911 /**
912  * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
913  * @hsotg: Programming view of DWC_otg controller.
914  * @offset: Register's offset where bit/bits must be set.
915  * @mask: Mask of the bit/bits which must be set.
916  * @timeout: Timeout to wait.
917  *
918  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
919  */
dwc2_hsotg_wait_bit_set(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)920 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
921 			    u32 timeout)
922 {
923 	u32 i;
924 
925 	for (i = 0; i < timeout; i++) {
926 		if (dwc2_readl(hsotg, offset) & mask)
927 			return 0;
928 		udelay(1);
929 	}
930 
931 	return -ETIMEDOUT;
932 }
933 
934 /**
935  * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
936  * @hsotg: Programming view of DWC_otg controller.
937  * @offset: Register's offset where bit/bits must be set.
938  * @mask: Mask of the bit/bits which must be set.
939  * @timeout: Timeout to wait.
940  *
941  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
942  */
dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)943 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
944 			      u32 timeout)
945 {
946 	u32 i;
947 
948 	for (i = 0; i < timeout; i++) {
949 		if (!(dwc2_readl(hsotg, offset) & mask))
950 			return 0;
951 		udelay(1);
952 	}
953 
954 	return -ETIMEDOUT;
955 }
956 
957 /*
958  * Initializes the FSLSPClkSel field of the HCFG register depending on the
959  * PHY type
960  */
dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg * hsotg)961 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
962 {
963 	u32 hcfg, val;
964 
965 	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
966 	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
967 	     hsotg->params.ulpi_fs_ls) ||
968 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
969 		/* Full speed PHY */
970 		val = HCFG_FSLSPCLKSEL_48_MHZ;
971 	} else {
972 		/* High speed PHY running at full speed or high speed */
973 		val = HCFG_FSLSPCLKSEL_30_60_MHZ;
974 	}
975 
976 	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
977 	hcfg = dwc2_readl(hsotg, HCFG);
978 	hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
979 	hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
980 	dwc2_writel(hsotg, hcfg, HCFG);
981 }
982 
dwc2_set_clock_switch_timer(struct dwc2_hsotg * hsotg)983 static void dwc2_set_clock_switch_timer(struct dwc2_hsotg *hsotg)
984 {
985 	u32 grstctl, gsnpsid, val = 0;
986 
987 	gsnpsid = dwc2_readl(hsotg, GSNPSID);
988 
989 	/*
990 	 * Applicable only to HSOTG core v5.00a or higher.
991 	 * Not applicable to HS/FS IOT devices.
992 	 */
993 	if ((gsnpsid & ~DWC2_CORE_REV_MASK) != DWC2_OTG_ID ||
994 	    gsnpsid < DWC2_CORE_REV_5_00a)
995 		return;
996 
997 	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI &&
998 	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) ||
999 	    (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1000 	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) ||
1001 	    (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED &&
1002 	     hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED)) {
1003 		val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS;
1004 	}
1005 
1006 	if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW &&
1007 	    hsotg->hw_params.hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED &&
1008 	    hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) {
1009 		val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147;
1010 	}
1011 
1012 	grstctl = dwc2_readl(hsotg, GRSTCTL);
1013 	grstctl &= ~GRSTCTL_CLOCK_SWITH_TIMER_MASK;
1014 	grstctl |= GRSTCTL_CLOCK_SWITH_TIMER(val);
1015 	dwc2_writel(hsotg, grstctl, GRSTCTL);
1016 }
1017 
dwc2_fs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1018 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1019 {
1020 	u32 usbcfg, ggpio, i2cctl;
1021 	int retval = 0;
1022 
1023 	/*
1024 	 * core_init() is now called on every switch so only call the
1025 	 * following for the first time through
1026 	 */
1027 	if (select_phy) {
1028 		dev_dbg(hsotg->dev, "FS PHY selected\n");
1029 
1030 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1031 		if (!(usbcfg & GUSBCFG_PHYSEL)) {
1032 			usbcfg |= GUSBCFG_PHYSEL;
1033 			dwc2_writel(hsotg, usbcfg, GUSBCFG);
1034 
1035 			dwc2_set_clock_switch_timer(hsotg);
1036 
1037 			/* Reset after a PHY select */
1038 			retval = dwc2_core_reset(hsotg, false);
1039 
1040 			if (retval) {
1041 				dev_err(hsotg->dev,
1042 					"%s: Reset failed, aborting", __func__);
1043 				return retval;
1044 			}
1045 		}
1046 
1047 		if (hsotg->params.activate_stm_fs_transceiver) {
1048 			ggpio = dwc2_readl(hsotg, GGPIO);
1049 			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1050 				dev_dbg(hsotg->dev, "Activating transceiver\n");
1051 				/*
1052 				 * STM32F4x9 uses the GGPIO register as general
1053 				 * core configuration register.
1054 				 */
1055 				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1056 				dwc2_writel(hsotg, ggpio, GGPIO);
1057 			}
1058 		}
1059 	}
1060 
1061 	/*
1062 	 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1063 	 * do this on HNP Dev/Host mode switches (done in dev_init and
1064 	 * host_init).
1065 	 */
1066 	if (dwc2_is_host_mode(hsotg))
1067 		dwc2_init_fs_ls_pclk_sel(hsotg);
1068 
1069 	if (hsotg->params.i2c_enable) {
1070 		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1071 
1072 		/* Program GUSBCFG.OtgUtmiFsSel to I2C */
1073 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1074 		usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1075 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1076 
1077 		/* Program GI2CCTL.I2CEn */
1078 		i2cctl = dwc2_readl(hsotg, GI2CCTL);
1079 		i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1080 		i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1081 		i2cctl &= ~GI2CCTL_I2CEN;
1082 		dwc2_writel(hsotg, i2cctl, GI2CCTL);
1083 		i2cctl |= GI2CCTL_I2CEN;
1084 		dwc2_writel(hsotg, i2cctl, GI2CCTL);
1085 	}
1086 
1087 	return retval;
1088 }
1089 
dwc2_hs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1090 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1091 {
1092 	u32 usbcfg, usbcfg_old;
1093 	int retval = 0;
1094 
1095 	if (!select_phy)
1096 		return 0;
1097 
1098 	usbcfg = dwc2_readl(hsotg, GUSBCFG);
1099 	usbcfg_old = usbcfg;
1100 
1101 	/*
1102 	 * HS PHY parameters. These parameters are preserved during soft reset
1103 	 * so only program the first time. Do a soft reset immediately after
1104 	 * setting phyif.
1105 	 */
1106 	switch (hsotg->params.phy_type) {
1107 	case DWC2_PHY_TYPE_PARAM_ULPI:
1108 		/* ULPI interface */
1109 		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1110 		usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1111 		usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1112 		if (hsotg->params.phy_ulpi_ddr)
1113 			usbcfg |= GUSBCFG_DDRSEL;
1114 
1115 		/* Set external VBUS indicator as needed. */
1116 		if (hsotg->params.oc_disable)
1117 			usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1118 				   GUSBCFG_INDICATORPASSTHROUGH);
1119 		break;
1120 	case DWC2_PHY_TYPE_PARAM_UTMI:
1121 		/* UTMI+ interface */
1122 		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1123 		usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1124 		if (hsotg->params.phy_utmi_width == 16)
1125 			usbcfg |= GUSBCFG_PHYIF16;
1126 		break;
1127 	default:
1128 		dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1129 		break;
1130 	}
1131 
1132 	if (usbcfg != usbcfg_old) {
1133 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1134 
1135 		/* Reset after setting the PHY parameters */
1136 		retval = dwc2_core_reset(hsotg, false);
1137 		if (retval) {
1138 			dev_err(hsotg->dev,
1139 				"%s: Reset failed, aborting", __func__);
1140 			return retval;
1141 		}
1142 	}
1143 
1144 	return retval;
1145 }
1146 
dwc2_set_turnaround_time(struct dwc2_hsotg * hsotg)1147 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1148 {
1149 	u32 usbcfg;
1150 
1151 	if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1152 		return;
1153 
1154 	usbcfg = dwc2_readl(hsotg, GUSBCFG);
1155 
1156 	usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1157 	if (hsotg->params.phy_utmi_width == 16)
1158 		usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1159 	else
1160 		usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1161 
1162 	dwc2_writel(hsotg, usbcfg, GUSBCFG);
1163 }
1164 
dwc2_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1165 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1166 {
1167 	u32 usbcfg;
1168 	u32 otgctl;
1169 	int retval = 0;
1170 
1171 	if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1172 	     hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1173 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1174 		/* If FS/LS mode with FS/LS PHY */
1175 		retval = dwc2_fs_phy_init(hsotg, select_phy);
1176 		if (retval)
1177 			return retval;
1178 	} else {
1179 		/* High speed PHY */
1180 		retval = dwc2_hs_phy_init(hsotg, select_phy);
1181 		if (retval)
1182 			return retval;
1183 
1184 		if (dwc2_is_device_mode(hsotg))
1185 			dwc2_set_turnaround_time(hsotg);
1186 	}
1187 
1188 	if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1189 	    hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1190 	    hsotg->params.ulpi_fs_ls) {
1191 		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1192 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1193 		usbcfg |= GUSBCFG_ULPI_FS_LS;
1194 		usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1195 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1196 	} else {
1197 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1198 		usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1199 		usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1200 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1201 	}
1202 
1203 	if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1204 		if (dwc2_is_host_mode(hsotg)) {
1205 			otgctl = readl(hsotg->regs + GOTGCTL);
1206 			otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1207 			writel(otgctl, hsotg->regs + GOTGCTL);
1208 		}
1209 	}
1210 
1211 	return retval;
1212 }
1213 
1214 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1215 MODULE_AUTHOR("Synopsys, Inc.");
1216 MODULE_LICENSE("Dual BSD/GPL");
1217