1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * Purpose: rf function code
7 *
8 * Author: Jerry Chen
9 *
10 * Date: Feb. 19, 2004
11 *
12 * Functions:
13 * IFRFbWriteEmbedded - Embedded write RF register via MAC
14 *
15 * Revision History:
16 * RobertYu 2005
17 * chester 2008
18 *
19 */
20
21 #include "mac.h"
22 #include "srom.h"
23 #include "rf.h"
24 #include "baseband.h"
25
26 #define BY_AL2230_REG_LEN 23 /* 24bit */
27 #define CB_AL2230_INIT_SEQ 15
28 #define SWITCH_CHANNEL_DELAY_AL2230 200 /* us */
29 #define AL2230_PWR_IDX_LEN 64
30
31 #define BY_AL7230_REG_LEN 23 /* 24bit */
32 #define CB_AL7230_INIT_SEQ 16
33 #define SWITCH_CHANNEL_DELAY_AL7230 200 /* us */
34 #define AL7230_PWR_IDX_LEN 64
35
36 static const unsigned long al2230_init_table[CB_AL2230_INIT_SEQ] = {
37 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
38 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
39 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
40 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
41 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
42 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
43 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
44 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
45 0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
46 0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
47 0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
48 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
49 0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
50 0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
51 0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
52 };
53
54 static const unsigned long al2230_channel_table0[CB_MAX_CHANNEL] = {
55 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
56 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
57 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
58 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
59 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
60 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
61 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
62 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
63 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
64 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
65 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
66 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
67 0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
68 0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */
69 };
70
71 static const unsigned long al2230_channel_table1[CB_MAX_CHANNEL] = {
72 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
73 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
74 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
75 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
76 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
77 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
78 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
79 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
80 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
81 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
82 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
83 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
84 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
85 0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */
86 };
87
88 static unsigned long al2230_power_table[AL2230_PWR_IDX_LEN] = {
89 0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
90 0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
91 0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
92 0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
93 0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
94 0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
95 0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
96 0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
97 0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
98 0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
99 0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
100 0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
101 0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
102 0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
103 0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
104 0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
105 0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
106 0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
107 0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
108 0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
109 0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
110 0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
111 0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
112 0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
113 0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
114 0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
115 0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
116 0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
117 0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
118 0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
119 0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
120 0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
121 0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
122 0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
123 0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
124 0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
125 0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
126 0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
127 0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
128 0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
129 0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
130 0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
131 0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
132 0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
133 0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
134 0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
135 0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
136 0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
137 0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
138 0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
139 0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
140 0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
141 0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
142 0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
143 0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
144 0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
145 0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
146 0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
147 0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
148 0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
149 0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
150 0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
151 0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
152 0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
153 };
154
155 /*
156 * Description: Write to IF/RF, by embedded programming
157 *
158 * Parameters:
159 * In:
160 * iobase - I/O base address
161 * dwData - data to write
162 * Out:
163 * none
164 *
165 * Return Value: true if succeeded; false if failed.
166 *
167 */
IFRFbWriteEmbedded(struct vnt_private * priv,unsigned long dwData)168 bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
169 {
170 void __iomem *iobase = priv->port_offset;
171 unsigned short ww;
172 unsigned long dwValue;
173
174 iowrite32((u32)dwData, iobase + MAC_REG_IFREGCTL);
175
176 /* W_MAX_TIMEOUT is the timeout period */
177 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
178 dwValue = ioread32(iobase + MAC_REG_IFREGCTL);
179 if (dwValue & IFREGCTL_DONE)
180 break;
181 }
182
183 if (ww == W_MAX_TIMEOUT)
184 return false;
185
186 return true;
187 }
188
189 /*
190 * Description: AIROHA IFRF chip init function
191 *
192 * Parameters:
193 * In:
194 * iobase - I/O base address
195 * Out:
196 * none
197 *
198 * Return Value: true if succeeded; false if failed.
199 *
200 */
RFbAL2230Init(struct vnt_private * priv)201 static bool RFbAL2230Init(struct vnt_private *priv)
202 {
203 void __iomem *iobase = priv->port_offset;
204 int ii;
205 bool ret;
206
207 ret = true;
208
209 /* 3-wire control for normal mode */
210 iowrite8(0, iobase + MAC_REG_SOFTPWRCTL);
211
212 vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL,
213 (SOFTPWRCTL_SWPECTI | SOFTPWRCTL_TXPEINV));
214 /* PLL Off */
215 vt6655_mac_word_reg_bits_off(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
216
217 /* patch abnormal AL2230 frequency output */
218 IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
219
220 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
221 ret &= IFRFbWriteEmbedded(priv, al2230_init_table[ii]);
222 MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */
223
224 /* PLL On */
225 vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
226
227 MACvTimer0MicroSDelay(priv, 150);/* 150us */
228 ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
229 MACvTimer0MicroSDelay(priv, 30);/* 30us */
230 ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
231 MACvTimer0MicroSDelay(priv, 30);/* 30us */
232 ret &= IFRFbWriteEmbedded(priv,
233 al2230_init_table[CB_AL2230_INIT_SEQ - 1]);
234
235 vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
236 SOFTPWRCTL_SWPE2 |
237 SOFTPWRCTL_SWPECTI |
238 SOFTPWRCTL_TXPEINV));
239
240 /* 3-wire control for power saving mode */
241 iowrite8(PSSIG_WPE3 | PSSIG_WPE2, iobase + MAC_REG_PSPWRSIG);
242
243 return ret;
244 }
245
RFbAL2230SelectChannel(struct vnt_private * priv,unsigned char byChannel)246 static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
247 {
248 void __iomem *iobase = priv->port_offset;
249 bool ret;
250
251 ret = true;
252
253 ret &= IFRFbWriteEmbedded(priv, al2230_channel_table0[byChannel - 1]);
254 ret &= IFRFbWriteEmbedded(priv, al2230_channel_table1[byChannel - 1]);
255
256 /* Set Channel[7] = 0 to tell H/W channel is changing now. */
257 iowrite8(byChannel & 0x7F, iobase + MAC_REG_CHANNEL);
258 MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230);
259 /* Set Channel[7] = 1 to tell H/W channel change is done. */
260 iowrite8(byChannel | 0x80, iobase + MAC_REG_CHANNEL);
261
262 return ret;
263 }
264
265 /*
266 * Description: RF init function
267 *
268 * Parameters:
269 * In:
270 * byBBType
271 * rf_type
272 * Out:
273 * none
274 *
275 * Return Value: true if succeeded; false if failed.
276 *
277 */
RFbInit(struct vnt_private * priv)278 bool RFbInit(struct vnt_private *priv)
279 {
280 bool ret = true;
281
282 switch (priv->rf_type) {
283 case RF_AIROHA:
284 case RF_AL2230S:
285 priv->max_pwr_level = AL2230_PWR_IDX_LEN;
286 ret = RFbAL2230Init(priv);
287 break;
288 case RF_NOTHING:
289 ret = true;
290 break;
291 default:
292 ret = false;
293 break;
294 }
295 return ret;
296 }
297
298 /*
299 * Description: Select channel
300 *
301 * Parameters:
302 * In:
303 * rf_type
304 * byChannel - Channel number
305 * Out:
306 * none
307 *
308 * Return Value: true if succeeded; false if failed.
309 *
310 */
RFbSelectChannel(struct vnt_private * priv,unsigned char rf_type,u16 byChannel)311 bool RFbSelectChannel(struct vnt_private *priv, unsigned char rf_type,
312 u16 byChannel)
313 {
314 bool ret = true;
315
316 switch (rf_type) {
317 case RF_AIROHA:
318 case RF_AL2230S:
319 ret = RFbAL2230SelectChannel(priv, byChannel);
320 break;
321 /*{{ RobertYu: 20050104 */
322 case RF_NOTHING:
323 ret = true;
324 break;
325 default:
326 ret = false;
327 break;
328 }
329 return ret;
330 }
331
332 /*
333 * Description: Write WakeProgSyn
334 *
335 * Parameters:
336 * In:
337 * priv - Device Structure
338 * rf_type - RF type
339 * channel - Channel number
340 *
341 * Return Value: true if succeeded; false if failed.
342 *
343 */
rf_write_wake_prog_syn(struct vnt_private * priv,unsigned char rf_type,u16 channel)344 bool rf_write_wake_prog_syn(struct vnt_private *priv, unsigned char rf_type,
345 u16 channel)
346 {
347 void __iomem *iobase = priv->port_offset;
348 int i;
349 unsigned char init_count = 0;
350 unsigned char sleep_count = 0;
351 unsigned short idx = MISCFIFO_SYNDATA_IDX;
352
353 iowrite16(0, iobase + MAC_REG_MISCFFNDEX);
354 switch (rf_type) {
355 case RF_AIROHA:
356 case RF_AL2230S:
357
358 if (channel > CB_MAX_CHANNEL_24G)
359 return false;
360
361 /* Init Reg + Channel Reg (2) */
362 init_count = CB_AL2230_INIT_SEQ + 2;
363 sleep_count = 0;
364
365 for (i = 0; i < CB_AL2230_INIT_SEQ; i++)
366 MACvSetMISCFifo(priv, idx++, al2230_init_table[i]);
367
368 MACvSetMISCFifo(priv, idx++, al2230_channel_table0[channel - 1]);
369 MACvSetMISCFifo(priv, idx++, al2230_channel_table1[channel - 1]);
370 break;
371
372 /* Need to check, PLLON need to be low for channel setting */
373
374 case RF_NOTHING:
375 return true;
376
377 default:
378 return false;
379 }
380
381 MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(sleep_count, init_count));
382
383 return true;
384 }
385
386 /*
387 * Description: Set Tx power
388 *
389 * Parameters:
390 * In:
391 * iobase - I/O base address
392 * dwRFPowerTable - RF Tx Power Setting
393 * Out:
394 * none
395 *
396 * Return Value: true if succeeded; false if failed.
397 *
398 */
RFbSetPower(struct vnt_private * priv,unsigned int rate,u16 uCH)399 bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH)
400 {
401 bool ret;
402 unsigned char byPwr = 0;
403 unsigned char byDec = 0;
404
405 if (priv->dwDiagRefCount != 0)
406 return true;
407
408 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL))
409 return false;
410
411 switch (rate) {
412 case RATE_1M:
413 case RATE_2M:
414 case RATE_5M:
415 case RATE_11M:
416 if (uCH > CB_MAX_CHANNEL_24G)
417 return false;
418
419 byPwr = priv->abyCCKPwrTbl[uCH];
420 break;
421 case RATE_6M:
422 case RATE_9M:
423 case RATE_12M:
424 case RATE_18M:
425 byPwr = priv->abyOFDMPwrTbl[uCH];
426 byDec = byPwr + 10;
427
428 if (byDec >= priv->max_pwr_level)
429 byDec = priv->max_pwr_level - 1;
430
431 byPwr = byDec;
432 break;
433 case RATE_24M:
434 case RATE_36M:
435 case RATE_48M:
436 case RATE_54M:
437 byPwr = priv->abyOFDMPwrTbl[uCH];
438 break;
439 }
440
441 if (priv->cur_pwr == byPwr)
442 return true;
443
444 ret = RFbRawSetPower(priv, byPwr, rate);
445 if (ret)
446 priv->cur_pwr = byPwr;
447
448 return ret;
449 }
450
451 /*
452 * Description: Set Tx power
453 *
454 * Parameters:
455 * In:
456 * iobase - I/O base address
457 * dwRFPowerTable - RF Tx Power Setting
458 * Out:
459 * none
460 *
461 * Return Value: true if succeeded; false if failed.
462 *
463 */
464
RFbRawSetPower(struct vnt_private * priv,unsigned char byPwr,unsigned int rate)465 bool RFbRawSetPower(struct vnt_private *priv, unsigned char byPwr,
466 unsigned int rate)
467 {
468 bool ret = true;
469
470 if (byPwr >= priv->max_pwr_level)
471 return false;
472
473 switch (priv->rf_type) {
474 case RF_AIROHA:
475 ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]);
476 if (rate <= RATE_11M)
477 ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
478 else
479 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
480
481 break;
482
483 case RF_AL2230S:
484 ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]);
485 if (rate <= RATE_11M) {
486 ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
487 ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
488 } else {
489 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
490 ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
491 }
492
493 break;
494
495 default:
496 break;
497 }
498 return ret;
499 }
500
501 /*
502 *
503 * Routine Description:
504 * Translate RSSI to dBm
505 *
506 * Parameters:
507 * In:
508 * priv - The adapter to be translated
509 * byCurrRSSI - RSSI to be translated
510 * Out:
511 * pdwdbm - Translated dbm number
512 *
513 * Return Value: none
514 *
515 */
516 void
RFvRSSITodBm(struct vnt_private * priv,unsigned char byCurrRSSI,long * pldBm)517 RFvRSSITodBm(struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm)
518 {
519 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
520 long b = (byCurrRSSI & 0x3F);
521 long a = 0;
522 unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
523
524 switch (priv->rf_type) {
525 case RF_AIROHA:
526 case RF_AL2230S:
527 a = abyAIROHARF[byIdx];
528 break;
529 default:
530 break;
531 }
532
533 *pldBm = -1 * (a + b * 2);
534 }
535
536