1 // SPDX-License-Identifier: GPL-2.0
2 /*****************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <drv_types.h>
9 #include "odm_precomp.h"
10
11 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */
12 #define PATH_S0 1 /* RF_PATH_B */
13 #define IDX_0xC94 0
14 #define IDX_0xC80 1
15 #define IDX_0xC14 0
16 #define IDX_0xCA0 1
17 #define KEY 0
18 #define VAL 1
19
20 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */
21 #define PATH_S1 0 /* RF_PATH_A */
22 #define IDX_0xC4C 2
23
24 /*---------------------------Define Local Constant---------------------------*/
25
26 /* In the case that we fail to read TxPowerTrack.txt, we use the table for
27 * 88E as the default table.
28 */
29 static u8 DeltaSwingTableIdx_2GA_N_8188E[] = {
30 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
31 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
32 };
33 static u8 DeltaSwingTableIdx_2GA_P_8188E[] = {
34 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4,
35 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9
36 };
37
38 /* 3 ============================================================ */
39 /* 3 Tx Power Tracking */
40 /* 3 ============================================================ */
41
42
setIqkMatrix_8723B(struct dm_odm_t * pDM_Odm,u8 OFDM_index,u8 RFPath,s32 IqkResult_X,s32 IqkResult_Y)43 static void setIqkMatrix_8723B(
44 struct dm_odm_t *pDM_Odm,
45 u8 OFDM_index,
46 u8 RFPath,
47 s32 IqkResult_X,
48 s32 IqkResult_Y
49 )
50 {
51 s32 ele_A = 0, ele_D, ele_C = 0, value32;
52
53 if (OFDM_index >= OFDM_TABLE_SIZE)
54 OFDM_index = OFDM_TABLE_SIZE-1;
55
56 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
57
58 /* new element A = element D x X */
59 if (IqkResult_X != 0) {
60 if ((IqkResult_X & 0x00000200) != 0) /* consider minus */
61 IqkResult_X = IqkResult_X | 0xFFFFFC00;
62 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
63
64 /* new element C = element D x Y */
65 if ((IqkResult_Y & 0x00000200) != 0)
66 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
67 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
68
69 /* if (RFPath == RF_PATH_A) */
70 switch (RFPath) {
71 case RF_PATH_A:
72 /* write new elements A, C, D to regC80 and regC94,
73 * element B is always 0
74 */
75 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
76 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
77
78 value32 = (ele_C&0x000003C0)>>6;
79 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
80
81 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
82 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32);
83 break;
84 case RF_PATH_B:
85 /* write new elements A, C, D to regC88 and regC9C,
86 * element B is always 0
87 */
88 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
89 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
90
91 value32 = (ele_C&0x000003C0)>>6;
92 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
93
94 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
95 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32);
96
97 break;
98 default:
99 break;
100 }
101 } else {
102 switch (RFPath) {
103 case RF_PATH_A:
104 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
106 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00);
107 break;
108
109 case RF_PATH_B:
110 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
111 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
112 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);
113 break;
114
115 default:
116 break;
117 }
118 }
119 }
120
121
setCCKFilterCoefficient(struct dm_odm_t * pDM_Odm,u8 CCKSwingIndex)122 static void setCCKFilterCoefficient(struct dm_odm_t *pDM_Odm, u8 CCKSwingIndex)
123 {
124 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
125 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);
126 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);
127 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);
128 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);
129 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);
130 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);
131 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);
132 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);
133 } else {
134 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);
135 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);
136 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);
137 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);
138 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);
139 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);
140 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);
141 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);
142 }
143 }
144
DoIQK_8723B(struct dm_odm_t * pDM_Odm,u8 DeltaThermalIndex,u8 ThermalValue,u8 Threshold)145 void DoIQK_8723B(
146 struct dm_odm_t *pDM_Odm,
147 u8 DeltaThermalIndex,
148 u8 ThermalValue,
149 u8 Threshold
150 )
151 {
152 }
153
154 /*-----------------------------------------------------------------------------
155 * Function: odm_TxPwrTrackSetPwr88E()
156 *
157 * Overview: 88E change all channel tx power according to flag.
158 * OFDM & CCK are all different.
159 *
160 * Input: NONE
161 *
162 * Output: NONE
163 *
164 * Return: NONE
165 *
166 * Revised History:
167 *When Who Remark
168 *04/23/2012 MHC Create Version 0.
169 *
170 *---------------------------------------------------------------------------*/
ODM_TxPwrTrackSetPwr_8723B(struct dm_odm_t * pDM_Odm,enum pwrtrack_method Method,u8 RFPath,u8 ChannelMappedIndex)171 void ODM_TxPwrTrackSetPwr_8723B(
172 struct dm_odm_t *pDM_Odm,
173 enum pwrtrack_method Method,
174 u8 RFPath,
175 u8 ChannelMappedIndex
176 )
177 {
178 struct adapter *Adapter = pDM_Odm->Adapter;
179 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
180 u8 PwrTrackingLimit_OFDM = 34; /* 0dB */
181 u8 PwrTrackingLimit_CCK = 28; /* 2dB */
182 u8 TxRate = 0xFF;
183 u8 Final_OFDM_Swing_Index = 0;
184 u8 Final_CCK_Swing_Index = 0;
185
186 {
187 u16 rate = *(pDM_Odm->pForcedDataRate);
188
189 if (!rate) { /* auto rate */
190 if (pDM_Odm->TxRate != 0xFF)
191 TxRate = HwRateToMRate(pDM_Odm->TxRate);
192 } else /* force rate */
193 TxRate = (u8)rate;
194
195 }
196
197 if (TxRate != 0xFF) {
198 /* 2 CCK */
199 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M))
200 PwrTrackingLimit_CCK = 28; /* 2dB */
201 /* 2 OFDM */
202 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M))
203 PwrTrackingLimit_OFDM = 36; /* 3dB */
204 else if (TxRate == MGN_54M)
205 PwrTrackingLimit_OFDM = 34; /* 2dB */
206
207 /* 2 HT */
208 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */
209 PwrTrackingLimit_OFDM = 38; /* 4dB */
210 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */
211 PwrTrackingLimit_OFDM = 36; /* 3dB */
212 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */
213 PwrTrackingLimit_OFDM = 34; /* 2dB */
214
215 else
216 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; /* Default OFDM index = 30 */
217 }
218
219 if (Method == TXAGC) {
220 struct adapter *Adapter = pDM_Odm->Adapter;
221
222 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
223
224 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
225 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
226
227 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
228 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
229 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
230 } else if (Method == BBSWING) {
231 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
232 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
233
234 /* Adjust BB swing by OFDM IQ matrix */
235 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
236 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
237 else if (Final_OFDM_Swing_Index <= 0)
238 Final_OFDM_Swing_Index = 0;
239
240 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
241 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
242 else if (pDM_Odm->BbSwingIdxCck <= 0)
243 Final_CCK_Swing_Index = 0;
244
245 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
246 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
247 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
248
249 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
250
251 } else if (Method == MIX_MODE) {
252 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
253 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
254
255 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */
256 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
257
258 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath,
259 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
260 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
261
262 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
263 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
264 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
265 } else if (Final_OFDM_Swing_Index <= 0) {
266 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
267
268 setIqkMatrix_8723B(pDM_Odm, 0, RFPath,
269 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
270 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
271
272 pDM_Odm->Modify_TxAGC_Flag_PathA = true;
273 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
274 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
275 } else {
276 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
277 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][0],
278 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[ChannelMappedIndex][1]);
279
280 if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */
281 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;
282 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
283 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
284 pDM_Odm->Modify_TxAGC_Flag_PathA = false;
285 }
286 }
287
288 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) {
289 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
290 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
291 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
292 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
293 } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */
294 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
295 setCCKFilterCoefficient(pDM_Odm, 0);
296 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true;
297 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
298 } else {
299 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
300
301 if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */
302 pDM_Odm->Remnant_CCKSwingIdx = 0;
303 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
304 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false;
305 }
306 }
307 } else
308 return; /* This method is not supported. */
309 }
310
GetDeltaSwingTable_8723B(struct dm_odm_t * pDM_Odm,u8 ** TemperatureUP_A,u8 ** TemperatureDOWN_A,u8 ** TemperatureUP_B,u8 ** TemperatureDOWN_B)311 static void GetDeltaSwingTable_8723B(
312 struct dm_odm_t *pDM_Odm,
313 u8 **TemperatureUP_A,
314 u8 **TemperatureDOWN_A,
315 u8 **TemperatureUP_B,
316 u8 **TemperatureDOWN_B
317 )
318 {
319 struct adapter *Adapter = pDM_Odm->Adapter;
320 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
321 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
322 u16 rate = *(pDM_Odm->pForcedDataRate);
323 u8 channel = pHalData->CurrentChannel;
324
325 if (1 <= channel && channel <= 14) {
326 if (IS_CCK_RATE(rate)) {
327 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
328 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
329 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
330 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
331 } else {
332 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
333 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
334 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
335 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
336 }
337 } else {
338 *TemperatureUP_A = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
339 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
340 *TemperatureUP_B = (u8 *)DeltaSwingTableIdx_2GA_P_8188E;
341 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E;
342 }
343 }
344
345
ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg * pConfig)346 void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *pConfig)
347 {
348 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
349 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
350 pConfig->Threshold_IQK = IQK_THRESHOLD;
351 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;
352 pConfig->RfPathCount = MAX_PATH_NUM_8723B;
353 pConfig->ThermalRegAddr = RF_T_METER_8723B;
354
355 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;
356 pConfig->DoIQK = DoIQK_8723B;
357 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;
358 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;
359 }
360
361 /* 1 7. IQK */
362 #define MAX_TOLERANCE 5
363
364 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_IQK_8723B(struct adapter * padapter,bool configPathB,u8 RF_Path)365 static u8 phy_PathA_IQK_8723B(
366 struct adapter *padapter, bool configPathB, u8 RF_Path
367 )
368 {
369 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;
370 u8 result = 0x00;
371
372 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
373 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
374
375 /* Save RF Path */
376 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
377
378 /* leave IQK mode */
379 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
380
381 /* enable path A PA in TXIQK mode */
382 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
383 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
384 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f);
385 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87);
386 /* disable path B PA in TXIQK mode */
387 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */
388 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */
389
390 /* 1 Tx IQK */
391 /* IQK setting */
392 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
393 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
394 /* path-A IQK setting */
395 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
396 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
397 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
398 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
399 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */
400 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
401 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
402 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
403 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
404
405 /* LO calibration setting */
406 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
407
408 /* enter IQK mode */
409 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
410
411 /* Ant switch */
412 if (configPathB || (RF_Path == 0))
413 /* wifi switch to S1 */
414 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
415 else
416 /* wifi switch to S0 */
417 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
418
419 /* GNT_BT = 0 */
420 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
421
422 /* One shot, path A LOK & IQK */
423 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
424 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
425
426 /* delay x ms */
427 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
428 mdelay(IQK_DELAY_TIME_8723B);
429
430 /* restore Ant Path */
431 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
432 /* GNT_BT = 1 */
433 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
434
435 /* leave IQK mode */
436 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
437
438
439 /* Check failed */
440 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
441 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
442 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
443
444
445 /* Allen 20131125 */
446 tmp = (regE9C & 0x03FF0000)>>16;
447 if ((tmp & 0x200) > 0)
448 tmp = 0x400 - tmp;
449
450 if (
451 !(regEAC & BIT28) &&
452 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
453 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
454 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
455 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
456 (tmp < 0xf)
457 )
458 result |= 0x01;
459 else /* if Tx not OK, ignore Rx */
460 return result;
461
462 return result;
463 }
464
465 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathA_RxIQK8723B(struct adapter * padapter,bool configPathB,u8 RF_Path)466 static u8 phy_PathA_RxIQK8723B(
467 struct adapter *padapter, bool configPathB, u8 RF_Path
468 )
469 {
470 u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB;
471 u8 result = 0x00;
472 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
473 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
474
475 /* Save RF Path */
476 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
477
478 /* leave IQK mode */
479 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
480 /* 1 Get TXIMR setting */
481 /* modify RXIQK mode table */
482 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
483 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
484 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
485 /* LNA2 off, PA on for Dcut */
486 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
487 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
488 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
489
490 /* IQK setting */
491 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
492 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
493
494 /* path-A IQK setting */
495 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
496 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
497 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
498 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
499
500 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
501 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
502 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
503 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
504 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
505
506 /* LO calibration setting */
507 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
508
509 /* enter IQK mode */
510 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
511
512 /* Ant switch */
513 if (configPathB || (RF_Path == 0))
514 /* wifi switch to S1 */
515 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
516 else
517 /* wifi switch to S0 */
518 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
519
520 /* GNT_BT = 0 */
521 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
522
523 /* One shot, path A LOK & IQK */
524 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
525 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
526
527 /* delay x ms */
528 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
529 mdelay(IQK_DELAY_TIME_8723B);
530
531 /* restore Ant Path */
532 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
533 /* GNT_BT = 1 */
534 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
535
536 /* leave IQK mode */
537 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
538
539 /* Check failed */
540 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
541 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
542 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
543
544 /* Allen 20131125 */
545 tmp = (regE9C & 0x03FF0000)>>16;
546 if ((tmp & 0x200) > 0)
547 tmp = 0x400 - tmp;
548
549 if (
550 !(regEAC & BIT28) &&
551 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
552 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
553 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
554 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
555 (tmp < 0xf)
556 )
557 result |= 0x01;
558 else /* if Tx not OK, ignore Rx */
559 return result;
560
561 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
562 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
563
564 /* modify RXIQK mode table */
565 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
566 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
567 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
568 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
569 /* LAN2 on, PA off for Dcut */
570 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
571 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
572
573 /* PA, PAD setting */
574 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
575 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f);
576
577
578 /* IQK setting */
579 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
580
581 /* path-A IQK setting */
582 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
583 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
584 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
585 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
586
587 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
588 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
589 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
590 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
591 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
592
593 /* LO calibration setting */
594 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
595
596 /* enter IQK mode */
597 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
598
599 /* Ant switch */
600 if (configPathB || (RF_Path == 0))
601 /* wifi switch to S1 */
602 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
603 else
604 /* wifi switch to S0 */
605 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
606
607 /* GNT_BT = 0 */
608 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
609
610 /* One shot, path A LOK & IQK */
611 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
612 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
613
614 /* delay x ms */
615 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */
616 mdelay(IQK_DELAY_TIME_8723B);
617
618 /* restore Ant Path */
619 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
620 /* GNT_BT = 1 */
621 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
622
623 /* leave IQK mode */
624 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
625
626 /* Check failed */
627 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
628 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
629
630 /* PA/PAD controlled by 0x0 */
631 /* leave IQK mode */
632 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
633 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780);
634
635 /* Allen 20131125 */
636 tmp = (regEAC & 0x03FF0000)>>16;
637 if ((tmp & 0x200) > 0)
638 tmp = 0x400 - tmp;
639
640 if (
641 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
642 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
643 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
644 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
645 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
646 (tmp < 0xf)
647 )
648 result |= 0x02;
649
650 return result;
651 }
652
653 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathB_IQK_8723B(struct adapter * padapter)654 static u8 phy_PathB_IQK_8723B(struct adapter *padapter)
655 {
656 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;
657 u8 result = 0x00;
658 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
659 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
660
661 /* Save RF Path */
662 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
663
664 /* leave IQK mode */
665 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
666
667 /* in TXIQK mode */
668 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */
669 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */
670 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */
671 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */
672 /* enable path B PA in TXIQK mode */
673 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
674 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
675
676
677
678 /* 1 Tx IQK */
679 /* IQK setting */
680 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
681 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
682 /* path-A IQK setting */
683 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
684 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
685 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
686 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
687
688 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */
689 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea);
690 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
691 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
692 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
693
694 /* LO calibration setting */
695 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
696
697 /* enter IQK mode */
698 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
699
700 /* switch to path B */
701 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
702 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
703
704 /* GNT_BT = 0 */
705 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
706
707 /* One shot, path B LOK & IQK */
708 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
709 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
710
711 /* delay x ms */
712 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
713 mdelay(IQK_DELAY_TIME_8723B);
714
715 /* restore Ant Path */
716 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
717 /* GNT_BT = 1 */
718 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
719
720 /* leave IQK mode */
721 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
722
723 /* Check failed */
724 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
725 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
726 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
727
728 /* Allen 20131125 */
729 tmp = (regE9C & 0x03FF0000)>>16;
730 if ((tmp & 0x200) > 0)
731 tmp = 0x400 - tmp;
732
733 if (
734 !(regEAC & BIT28) &&
735 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
736 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
737 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
738 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
739 (tmp < 0xf)
740 )
741 result |= 0x01;
742
743 return result;
744 }
745
746 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
phy_PathB_RxIQK8723B(struct adapter * padapter,bool configPathB)747 static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB)
748 {
749 u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;
750 u8 result = 0x00;
751 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
752 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
753
754 /* Save RF Path */
755 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord);
756 /* leave IQK mode */
757 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
758
759 /* switch to path B */
760 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
761 /* modify RXIQK mode table */
762 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
763 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
764 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
765 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
766 /* open PA S1 & SMIXER */
767 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
768 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd);
769
770
771 /* IQK setting */
772 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
773 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
774
775
776 /* path-B IQK setting */
777 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
778 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
779 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
780 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
781
782 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */
783 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0);
784 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
785 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
786 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
787
788 /* LO calibration setting */
789 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
790
791 /* enter IQK mode */
792 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
793
794 /* switch to path B */
795 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
796 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
797
798 /* GNT_BT = 0 */
799 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
800
801 /* One shot, path B TXIQK @ RXIQK */
802 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
803 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
804
805
806 /* delay x ms */
807 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
808 mdelay(IQK_DELAY_TIME_8723B);
809
810 /* restore Ant Path */
811 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
812 /* GNT_BT = 1 */
813 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
814
815 /* leave IQK mode */
816 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
817
818 /* Check failed */
819 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
820 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
821 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
822
823 /* Allen 20131125 */
824 tmp = (regE9C & 0x03FF0000)>>16;
825 if ((tmp & 0x200) > 0)
826 tmp = 0x400 - tmp;
827
828 if (
829 !(regEAC & BIT28) &&
830 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
831 (((regE9C & 0x03FF0000)>>16) != 0x42) &&
832 (((regE94 & 0x03FF0000)>>16) < 0x110) &&
833 (((regE94 & 0x03FF0000)>>16) > 0xf0) &&
834 (tmp < 0xf)
835 )
836 result |= 0x01;
837 else /* if Tx not OK, ignore Rx */
838 return result;
839
840 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
841 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp);
842
843 /* modify RXIQK mode table */
844 /* 20121009, Kordan> RF Mode = 3 */
845 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
846 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
847 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
848 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
849 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
850 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */
851
852 /* open PA S1 & close SMIXER */
853 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
854 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd);
855
856 /* PA, PAD setting */
857 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */
858 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */
859
860 /* IQK setting */
861 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
862
863 /* path-B IQK setting */
864 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
865 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
866 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
867 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
868
869 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
870 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */
871 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f);
872 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
873 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
874
875 /* LO calibration setting */
876 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
877
878 /* enter IQK mode */
879 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
880
881 /* switch to path B */
882 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
883 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */
884
885 /* GNT_BT = 0 */
886 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800);
887
888 /* One shot, path B LOK & IQK */
889 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
890 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
891
892 /* delay x ms */
893 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
894 mdelay(IQK_DELAY_TIME_8723B);
895
896 /* restore Ant Path */
897 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB);
898 /* GNT_BT = 1 */
899 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800);
900
901 /* leave IQK mode */
902 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
903
904 /* Check failed */
905 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
906 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
907
908 /* PA/PAD controlled by 0x0 */
909 /* leave IQK mode */
910 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
911 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
912
913
914
915 /* Allen 20131125 */
916 tmp = (regEAC & 0x03FF0000)>>16;
917 if ((tmp & 0x200) > 0)
918 tmp = 0x400 - tmp;
919
920 if (
921 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
922 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
923 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
924 (((regEA4 & 0x03FF0000)>>16) < 0x110) &&
925 (((regEA4 & 0x03FF0000)>>16) > 0xf0) &&
926 (tmp < 0xf)
927 )
928 result |= 0x02;
929
930 return result;
931 }
932
_PHY_PathAFillIQKMatrix8723B(struct adapter * padapter,bool bIQKOK,s32 result[][8],u8 final_candidate,bool bTxOnly)933 static void _PHY_PathAFillIQKMatrix8723B(
934 struct adapter *padapter,
935 bool bIQKOK,
936 s32 result[][8],
937 u8 final_candidate,
938 bool bTxOnly
939 )
940 {
941 u32 Oldval_0, X, TX0_A, reg;
942 s32 Y, TX0_C;
943 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
944 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
945
946 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
947
948 if (final_candidate == 0xFF)
949 return;
950
951 else if (bIQKOK) {
952 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
953
954 X = result[final_candidate][0];
955 if ((X & 0x00000200) != 0)
956 X = X | 0xFFFFFC00;
957 TX0_A = (X * Oldval_0) >> 8;
958 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
959
960 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1));
961
962 Y = result[final_candidate][1];
963 if ((Y & 0x00000200) != 0)
964 Y = Y | 0xFFFFFC00;
965
966 /* 2 Tx IQC */
967 TX0_C = (Y * Oldval_0) >> 8;
968 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
969 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
970 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord);
971
972 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
973 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
974 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord);
975
976 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1));
977 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
978 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
979
980 if (bTxOnly) {
981 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
982 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
983 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
984 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
985 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
986 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
987 return;
988 }
989
990 reg = result[final_candidate][2];
991
992 /* 2 Rx IQC */
993 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
994 reg = result[final_candidate][3] & 0x3F;
995 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
996 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
997 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord);
998
999 reg = (result[final_candidate][3] >> 6) & 0xF;
1000 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
1001 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1002 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1003
1004 }
1005 }
1006
_PHY_PathBFillIQKMatrix8723B(struct adapter * padapter,bool bIQKOK,s32 result[][8],u8 final_candidate,bool bTxOnly)1007 static void _PHY_PathBFillIQKMatrix8723B(
1008 struct adapter *padapter,
1009 bool bIQKOK,
1010 s32 result[][8],
1011 u8 final_candidate,
1012 bool bTxOnly /* do Tx only */
1013 )
1014 {
1015 u32 Oldval_1, X, TX1_A, reg;
1016 s32 Y, TX1_C;
1017 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1018 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1019
1020 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1021
1022 if (final_candidate == 0xFF)
1023 return;
1024
1025 else if (bIQKOK) {
1026 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1027
1028 X = result[final_candidate][4];
1029 if ((X & 0x00000200) != 0)
1030 X = X | 0xFFFFFC00;
1031 TX1_A = (X * Oldval_1) >> 8;
1032
1033 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
1034
1035 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1));
1036
1037 Y = result[final_candidate][5];
1038 if ((Y & 0x00000200) != 0)
1039 Y = Y | 0xFFFFFC00;
1040
1041 TX1_C = (Y * Oldval_1) >> 8;
1042
1043 /* 2 Tx IQC */
1044 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
1045 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */
1046 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */
1047 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1048 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord);
1049
1050 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
1051 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1052 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord);
1053
1054 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1));
1055 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1056 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord);
1057
1058 if (bTxOnly) {
1059 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1060 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */
1061 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
1062 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1063 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord);
1064 return;
1065 }
1066
1067 /* 2 Rx IQC */
1068 reg = result[final_candidate][6];
1069 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
1070 reg = result[final_candidate][7] & 0x3F;
1071 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
1072 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1073 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord);
1074
1075 reg = (result[final_candidate][7] >> 6) & 0xF;
1076 /* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */
1077 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1078 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff);
1079 }
1080 }
1081
1082 /* */
1083 /* 2011/07/26 MH Add an API for testing IQK fail case. */
1084 /* */
1085 /* MP Already declare in odm.c */
1086
ODM_SetIQCbyRFpath(struct dm_odm_t * pDM_Odm,u32 RFpath)1087 void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath)
1088 {
1089
1090 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1091
1092 if (
1093 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) &&
1094 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) &&
1095 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) &&
1096 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0)
1097 ) {
1098 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */
1099 /* S0 TX IQC */
1100 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);
1101 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);
1102 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);
1103 /* S0 RX IQC */
1104 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);
1105 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);
1106 } else {
1107 /* S1 TX IQC */
1108 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);
1109 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);
1110 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);
1111 /* S1 RX IQC */
1112 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);
1113 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);
1114 }
1115 }
1116 }
1117
ODM_CheckPowerStatus(struct adapter * Adapter)1118 static bool ODM_CheckPowerStatus(struct adapter *Adapter)
1119 {
1120 return true;
1121 }
1122
_PHY_SaveADDARegisters8723B(struct adapter * padapter,u32 * ADDAReg,u32 * ADDABackup,u32 RegisterNum)1123 static void _PHY_SaveADDARegisters8723B(
1124 struct adapter *padapter,
1125 u32 *ADDAReg,
1126 u32 *ADDABackup,
1127 u32 RegisterNum
1128 )
1129 {
1130 u32 i;
1131 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1132 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1133
1134 if (!ODM_CheckPowerStatus(padapter))
1135 return;
1136
1137 for (i = 0 ; i < RegisterNum ; i++) {
1138 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord);
1139 }
1140 }
1141
1142
_PHY_SaveMACRegisters8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1143 static void _PHY_SaveMACRegisters8723B(
1144 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1145 )
1146 {
1147 u32 i;
1148 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1149 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1150
1151 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1152 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]);
1153 }
1154 MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]);
1155
1156 }
1157
1158
_PHY_ReloadADDARegisters8723B(struct adapter * padapter,u32 * ADDAReg,u32 * ADDABackup,u32 RegiesterNum)1159 static void _PHY_ReloadADDARegisters8723B(
1160 struct adapter *padapter,
1161 u32 *ADDAReg,
1162 u32 *ADDABackup,
1163 u32 RegiesterNum
1164 )
1165 {
1166 u32 i;
1167 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1168 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1169
1170 for (i = 0 ; i < RegiesterNum; i++) {
1171 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1172 }
1173 }
1174
_PHY_ReloadMACRegisters8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1175 static void _PHY_ReloadMACRegisters8723B(
1176 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1177 )
1178 {
1179 u32 i;
1180
1181 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1182 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]);
1183 }
1184 rtw_write32(padapter, MACReg[i], MACBackup[i]);
1185 }
1186
1187
_PHY_PathADDAOn8723B(struct adapter * padapter,u32 * ADDAReg,bool is2T)1188 static void _PHY_PathADDAOn8723B(
1189 struct adapter *padapter,
1190 u32 *ADDAReg,
1191 bool is2T
1192 )
1193 {
1194 u32 pathOn;
1195 u32 i;
1196 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1197 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1198
1199 pathOn = 0x01c00014;
1200 if (!is2T) {
1201 pathOn = 0x01c00014;
1202 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014);
1203 } else {
1204 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn);
1205 }
1206
1207 for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
1208 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn);
1209 }
1210
1211 }
1212
_PHY_MACSettingCalibration8723B(struct adapter * padapter,u32 * MACReg,u32 * MACBackup)1213 static void _PHY_MACSettingCalibration8723B(
1214 struct adapter *padapter, u32 *MACReg, u32 *MACBackup
1215 )
1216 {
1217 u32 i = 0;
1218 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1219 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1220
1221 rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F);
1222
1223 for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
1224 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
1225 }
1226 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
1227
1228 }
1229
phy_SimularityCompare_8723B(struct adapter * padapter,s32 result[][8],u8 c1,u8 c2)1230 static bool phy_SimularityCompare_8723B(
1231 struct adapter *padapter,
1232 s32 result[][8],
1233 u8 c1,
1234 u8 c2
1235 )
1236 {
1237 u32 i, j, diff, SimularityBitMap, bound = 0;
1238 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
1239 bool bResult = true;
1240 s32 tmp1 = 0, tmp2 = 0;
1241
1242 bound = 8;
1243 SimularityBitMap = 0;
1244
1245 for (i = 0; i < bound; i++) {
1246
1247 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
1248 if ((result[c1][i] & 0x00000200) != 0)
1249 tmp1 = result[c1][i] | 0xFFFFFC00;
1250 else
1251 tmp1 = result[c1][i];
1252
1253 if ((result[c2][i] & 0x00000200) != 0)
1254 tmp2 = result[c2][i] | 0xFFFFFC00;
1255 else
1256 tmp2 = result[c2][i];
1257 } else {
1258 tmp1 = result[c1][i];
1259 tmp2 = result[c2][i];
1260 }
1261
1262 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1263
1264 if (diff > MAX_TOLERANCE) {
1265 if ((i == 2 || i == 6) && !SimularityBitMap) {
1266 if (result[c1][i]+result[c1][i+1] == 0)
1267 final_candidate[(i/4)] = c2;
1268 else if (result[c2][i]+result[c2][i+1] == 0)
1269 final_candidate[(i/4)] = c1;
1270 else
1271 SimularityBitMap = SimularityBitMap|(1<<i);
1272 } else
1273 SimularityBitMap = SimularityBitMap|(1<<i);
1274 }
1275 }
1276
1277 if (SimularityBitMap == 0) {
1278 for (i = 0; i < (bound/4); i++) {
1279 if (final_candidate[i] != 0xFF) {
1280 for (j = i*4; j < (i+1)*4-2; j++)
1281 result[3][j] = result[final_candidate[i]][j];
1282 bResult = false;
1283 }
1284 }
1285 return bResult;
1286 } else {
1287
1288 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */
1289 for (i = 0; i < 2; i++)
1290 result[3][i] = result[c1][i];
1291 }
1292
1293 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */
1294 for (i = 2; i < 4; i++)
1295 result[3][i] = result[c1][i];
1296 }
1297
1298 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */
1299 for (i = 4; i < 6; i++)
1300 result[3][i] = result[c1][i];
1301 }
1302
1303 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */
1304 for (i = 6; i < 8; i++)
1305 result[3][i] = result[c1][i];
1306 }
1307 return false;
1308 }
1309 }
1310
1311
1312
phy_IQCalibrate_8723B(struct adapter * padapter,s32 result[][8],u8 t,bool is2T,u8 RF_Path)1313 static void phy_IQCalibrate_8723B(
1314 struct adapter *padapter,
1315 s32 result[][8],
1316 u8 t,
1317 bool is2T,
1318 u8 RF_Path
1319 )
1320 {
1321 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1322 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1323
1324 u32 i;
1325 u8 PathAOK, PathBOK;
1326 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0);
1327 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0);
1328 u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
1329 rFPGA0_XCD_SwitchControl,
1330 rBlue_Tooth,
1331 rRx_Wait_CCA,
1332 rTx_CCK_RFON,
1333 rTx_CCK_BBON,
1334 rTx_OFDM_RFON,
1335 rTx_OFDM_BBON,
1336 rTx_To_Rx,
1337 rTx_To_Tx,
1338 rRx_CCK,
1339 rRx_OFDM,
1340 rRx_Wait_RIFS,
1341 rRx_TO_Rx,
1342 rStandby,
1343 rSleep,
1344 rPMPD_ANAEN
1345 };
1346 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1347 REG_TXPAUSE,
1348 REG_BCN_CTRL,
1349 REG_BCN_CTRL_1,
1350 REG_GPIO_MUXCFG
1351 };
1352
1353 /* since 92C & 92D have the different define in IQK_BB_REG */
1354 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1355 rOFDM0_TRxPathEnable,
1356 rOFDM0_TRMuxPar,
1357 rFPGA0_XCD_RFInterfaceSW,
1358 rConfig_AntA,
1359 rConfig_AntB,
1360 rFPGA0_XAB_RFInterfaceSW,
1361 rFPGA0_XA_RFInterfaceOE,
1362 rFPGA0_XB_RFInterfaceOE,
1363 rCCK0_AFESetting
1364 };
1365 const u32 retryCount = 2;
1366
1367 /* Note: IQ calibration must be performed after loading */
1368 /* PHY_REG.txt , and radio_a, radio_b.txt */
1369
1370 /* u32 bbvalue; */
1371
1372 if (t == 0) {
1373
1374 /* Save ADDA parameters, turn Path A ADDA on */
1375 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1376 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1377 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1378 }
1379
1380 _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T);
1381
1382 /* no serial mode */
1383
1384 /* save RF path for 8723B */
1385 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1386 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
1387
1388 /* MAC settings */
1389 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1390
1391 /* BB setting */
1392 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */
1393 PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf);
1394 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1395 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1396 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1397
1398
1399 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
1400 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
1401 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
1402 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
1403
1404
1405 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
1406
1407 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1408 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1409 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
1410 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1411 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
1412 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
1413 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
1414
1415 /* path A TX IQK */
1416 for (i = 0 ; i < retryCount ; i++) {
1417 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path);
1418 /* if (PathAOK == 0x03) { */
1419 if (PathAOK == 0x01) {
1420 /* Path A Tx IQK Success */
1421 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1422 pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x8, bRFRegOffsetMask);
1423
1424 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1425 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1426 break;
1427 }
1428 }
1429
1430 /* path A RXIQK */
1431 for (i = 0 ; i < retryCount ; i++) {
1432 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path);
1433 if (PathAOK == 0x03) {
1434 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1435 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1436 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1437 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1438 break;
1439 }
1440 }
1441
1442 if (0x00 == PathAOK) {
1443 }
1444
1445 /* path B IQK */
1446 if (is2T) {
1447
1448 /* path B TX IQK */
1449 for (i = 0 ; i < retryCount ; i++) {
1450 PathBOK = phy_PathB_IQK_8723B(padapter);
1451 if (PathBOK == 0x01) {
1452 /* Path B Tx IQK Success */
1453 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1454 pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_B, 0x8, bRFRegOffsetMask);
1455
1456 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1457 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1458 break;
1459 }
1460 }
1461
1462 /* path B RX IQK */
1463 for (i = 0 ; i < retryCount ; i++) {
1464 PathBOK = phy_PathB_RxIQK8723B(padapter, is2T);
1465 if (PathBOK == 0x03) {
1466 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1467 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */
1468 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1469 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1470 break;
1471 }
1472 }
1473
1474 /* Allen end */
1475 }
1476
1477 /* Back to BB mode, load original value */
1478 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0);
1479
1480 if (t != 0) {
1481 /* Reload ADDA power saving parameters */
1482 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1483
1484 /* Reload MAC parameters */
1485 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1486
1487 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1488
1489 /* Reload RF path */
1490 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1491 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1492
1493 /* Allen initial gain 0xc50 */
1494 /* Restore RX initial gain */
1495 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50);
1496 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50);
1497 if (is2T) {
1498 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50);
1499 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58);
1500 }
1501
1502 /* load 0xe30 IQC default value */
1503 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1504 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1505
1506 }
1507
1508 }
1509
1510
phy_LCCalibrate_8723B(struct dm_odm_t * pDM_Odm,bool is2T)1511 static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
1512 {
1513 u8 tmpReg;
1514 u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal;
1515 struct adapter *padapter = pDM_Odm->Adapter;
1516
1517 /* Check continuous TX and Packet TX */
1518 tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03);
1519
1520 if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
1521 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
1522 else /* Deal with Packet TX case */
1523 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */
1524
1525 if ((tmpReg&0x70) != 0) {
1526 /* 1. Read original RF mode */
1527 /* Path-A */
1528 RF_Amode = PHY_QueryRFReg(padapter, RF_PATH_A, RF_AC, bMask12Bits);
1529
1530 /* Path-B */
1531 if (is2T)
1532 RF_Bmode = PHY_QueryRFReg(padapter, RF_PATH_B, RF_AC, bMask12Bits);
1533
1534 /* 2. Set RF mode = standby mode */
1535 /* Path-A */
1536 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1537
1538 /* Path-B */
1539 if (is2T)
1540 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1541 }
1542
1543 /* 3. Read RF reg18 */
1544 LC_Cal = PHY_QueryRFReg(padapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
1545
1546 /* 4. Set LC calibration begin bit15 */
1547 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */
1548 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1549
1550 mdelay(100);
1551
1552 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */
1553
1554 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */
1555 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) {
1556 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
1557 }
1558
1559 /* Restore original situation */
1560 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */
1561 /* Path-A */
1562 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg);
1563 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1564
1565 /* Path-B */
1566 if (is2T)
1567 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1568 } else /* Deal with Packet TX case */
1569 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00);
1570 }
1571
1572 /* IQK version:V2.5 20140123 */
1573 /* IQK is controlled by Is2ant, RF path */
PHY_IQCalibrate_8723B(struct adapter * padapter,bool bReCovery,bool bRestore,bool Is2ant,u8 RF_Path)1574 void PHY_IQCalibrate_8723B(
1575 struct adapter *padapter,
1576 bool bReCovery,
1577 bool bRestore,
1578 bool Is2ant, /* false:1ant, true:2-ant */
1579 u8 RF_Path /* 0:S1, 1:S0 */
1580 )
1581 {
1582 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1583
1584 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1585
1586 s32 result[4][8]; /* last is final result */
1587 u8 i, final_candidate;
1588 bool bPathAOK, bPathBOK;
1589 s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC, RegEC4, RegTmp = 0;
1590 bool is12simular, is13simular, is23simular;
1591 bool bSingleTone = false, bCarrierSuppression = false;
1592 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1593 rOFDM0_XARxIQImbalance,
1594 rOFDM0_XBRxIQImbalance,
1595 rOFDM0_ECCAThreshold,
1596 rOFDM0_AGCRSSITable,
1597 rOFDM0_XATxIQImbalance,
1598 rOFDM0_XBTxIQImbalance,
1599 rOFDM0_XCTxAFE,
1600 rOFDM0_XDTxAFE,
1601 rOFDM0_RxIQExtAnta
1602 };
1603 /* u32 Path_SEL_BB = 0; */
1604 u32 GNT_BT_default;
1605
1606 if (!ODM_CheckPowerStatus(padapter))
1607 return;
1608
1609 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1610 return;
1611
1612 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1613 if (bSingleTone || bCarrierSuppression)
1614 return;
1615
1616 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
1617 return;
1618
1619
1620 pDM_Odm->RFCalibrateInfo.bIQKInProgress = true;
1621
1622 if (bRestore) {
1623 u32 offset, data;
1624 u8 path, bResult = SUCCESS;
1625 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo;
1626
1627 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_PATH_B;
1628
1629 /* Restore TX IQK */
1630 for (i = 0; i < 3; ++i) {
1631 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
1632 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
1633 if ((offset == 0) || (data == 0)) {
1634 bResult = FAIL;
1635 break;
1636 }
1637 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1638 }
1639
1640 /* Restore RX IQK */
1641 for (i = 0; i < 2; ++i) {
1642 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
1643 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
1644 if ((offset == 0) || (data == 0)) {
1645 bResult = FAIL;
1646 break;
1647 }
1648 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data);
1649 }
1650
1651 if (pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A] == 0) {
1652 bResult = FAIL;
1653 } else {
1654 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_A]);
1655 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[RF_PATH_B]);
1656 }
1657
1658 if (bResult == SUCCESS)
1659 return;
1660 }
1661
1662 if (bReCovery) {
1663 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1664 return;
1665 }
1666
1667 /* save default GNT_BT */
1668 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord);
1669 /* Save RF Path */
1670 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */
1671 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff); */
1672
1673 /* set GNT_BT = 0, pause BT traffic */
1674 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1675 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
1676
1677
1678 for (i = 0; i < 8; i++) {
1679 result[0][i] = 0;
1680 result[1][i] = 0;
1681 result[2][i] = 0;
1682 result[3][i] = 0;
1683 }
1684
1685 final_candidate = 0xff;
1686 bPathAOK = false;
1687 bPathBOK = false;
1688 is12simular = false;
1689 is23simular = false;
1690 is13simular = false;
1691
1692
1693 for (i = 0; i < 3; i++) {
1694 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path);
1695
1696 if (i == 1) {
1697 is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1);
1698 if (is12simular) {
1699 final_candidate = 0;
1700 break;
1701 }
1702 }
1703
1704 if (i == 2) {
1705 is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2);
1706 if (is13simular) {
1707 final_candidate = 0;
1708
1709 break;
1710 }
1711
1712 is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2);
1713 if (is23simular) {
1714 final_candidate = 1;
1715 } else {
1716 for (i = 0; i < 8; i++)
1717 RegTmp += result[3][i];
1718
1719 if (RegTmp != 0)
1720 final_candidate = 3;
1721 else
1722 final_candidate = 0xFF;
1723 }
1724 }
1725 }
1726
1727 for (i = 0; i < 4; i++) {
1728 RegE94 = result[i][0];
1729 RegE9C = result[i][1];
1730 RegEA4 = result[i][2];
1731 RegEB4 = result[i][4];
1732 RegEBC = result[i][5];
1733 RegEC4 = result[i][6];
1734 }
1735
1736 if (final_candidate != 0xff) {
1737 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
1738 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
1739 RegEA4 = result[final_candidate][2];
1740 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
1741 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
1742 RegEC4 = result[final_candidate][6];
1743 bPathAOK = bPathBOK = true;
1744 } else {
1745 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */
1746 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */
1747 }
1748
1749 {
1750 if (RegE94 != 0)
1751 _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
1752 }
1753 {
1754 if (RegEB4 != 0)
1755 _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
1756 }
1757
1758 /* To Fix BSOD when final_candidate is 0xff */
1759 /* by sherry 20120321 */
1760 if (final_candidate < 4) {
1761 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
1762 pDM_Odm->RFCalibrateInfo.iqk_matrix_regs_setting_value[0][i] = result[final_candidate][i];
1763 }
1764
1765 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
1766
1767 /* restore GNT_BT */
1768 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default);
1769 /* Restore RF Path */
1770 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */
1771 /* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */
1772
1773 /* Resotr RX mode table parameter */
1774 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1775 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000);
1776 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1777 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177);
1778 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
1779 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd);
1780
1781 /* set GNT_BT = HW control */
1782 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
1783 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */
1784
1785 if (Is2ant) {
1786 if (RF_Path == 0x0) /* S1 */
1787 ODM_SetIQCbyRFpath(pDM_Odm, 0);
1788 else /* S0 */
1789 ODM_SetIQCbyRFpath(pDM_Odm, 1);
1790 }
1791
1792 pDM_Odm->RFCalibrateInfo.bIQKInProgress = false;
1793 }
1794
1795
PHY_LCCalibrate_8723B(struct dm_odm_t * pDM_Odm)1796 void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm)
1797 {
1798 bool bSingleTone = false, bCarrierSuppression = false;
1799 u32 timeout = 2000, timecount = 0;
1800
1801 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
1802 return;
1803
1804 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
1805 if (bSingleTone || bCarrierSuppression)
1806 return;
1807
1808 while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) {
1809 mdelay(50);
1810 timecount += 50;
1811 }
1812
1813 pDM_Odm->RFCalibrateInfo.bLCKInProgress = true;
1814
1815
1816 phy_LCCalibrate_8723B(pDM_Odm, false);
1817
1818
1819 pDM_Odm->RFCalibrateInfo.bLCKInProgress = false;
1820 }
1821