1  // SPDX-License-Identifier: GPL-2.0-or-later
2  /*
3   * An RTC driver for Allwinner A31/A23
4   *
5   * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
6   *
7   * based on rtc-sunxi.c
8   *
9   * An RTC driver for Allwinner A10/A20
10   *
11   * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12   */
13  
14  #include <linux/clk.h>
15  #include <linux/clk-provider.h>
16  #include <linux/clk/sunxi-ng.h>
17  #include <linux/delay.h>
18  #include <linux/err.h>
19  #include <linux/fs.h>
20  #include <linux/init.h>
21  #include <linux/interrupt.h>
22  #include <linux/io.h>
23  #include <linux/kernel.h>
24  #include <linux/module.h>
25  #include <linux/of.h>
26  #include <linux/of_address.h>
27  #include <linux/platform_device.h>
28  #include <linux/rtc.h>
29  #include <linux/slab.h>
30  #include <linux/types.h>
31  
32  /* Control register */
33  #define SUN6I_LOSC_CTRL				0x0000
34  #define SUN6I_LOSC_CTRL_KEY			(0x16aa << 16)
35  #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS		BIT(15)
36  #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC		BIT(9)
37  #define SUN6I_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
38  #define SUN6I_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
39  #define SUN6I_LOSC_CTRL_EXT_LOSC_EN		BIT(4)
40  #define SUN6I_LOSC_CTRL_EXT_OSC			BIT(0)
41  #define SUN6I_LOSC_CTRL_ACC_MASK		GENMASK(9, 7)
42  
43  #define SUN6I_LOSC_CLK_PRESCAL			0x0008
44  
45  /* RTC */
46  #define SUN6I_RTC_YMD				0x0010
47  #define SUN6I_RTC_HMS				0x0014
48  
49  /* Alarm 0 (counter) */
50  #define SUN6I_ALRM_COUNTER			0x0020
51  /* This holds the remaining alarm seconds on older SoCs (current value) */
52  #define SUN6I_ALRM_COUNTER_HMS			0x0024
53  #define SUN6I_ALRM_EN				0x0028
54  #define SUN6I_ALRM_EN_CNT_EN			BIT(0)
55  #define SUN6I_ALRM_IRQ_EN			0x002c
56  #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)
57  #define SUN6I_ALRM_IRQ_STA			0x0030
58  #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0)
59  
60  /* Alarm 1 (wall clock) */
61  #define SUN6I_ALRM1_EN				0x0044
62  #define SUN6I_ALRM1_IRQ_EN			0x0048
63  #define SUN6I_ALRM1_IRQ_STA			0x004c
64  #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND	BIT(0)
65  
66  /* Alarm config */
67  #define SUN6I_ALARM_CONFIG			0x0050
68  #define SUN6I_ALARM_CONFIG_WAKEUP		BIT(0)
69  
70  #define SUN6I_LOSC_OUT_GATING			0x0060
71  #define SUN6I_LOSC_OUT_GATING_EN_OFFSET		0
72  
73  /* General-purpose data */
74  #define SUN6I_GP_DATA				0x0100
75  #define SUN6I_GP_DATA_SIZE			0x20
76  
77  /*
78   * Get date values
79   */
80  #define SUN6I_DATE_GET_DAY_VALUE(x)		((x)  & 0x0000001f)
81  #define SUN6I_DATE_GET_MON_VALUE(x)		(((x) & 0x00000f00) >> 8)
82  #define SUN6I_DATE_GET_YEAR_VALUE(x)		(((x) & 0x003f0000) >> 16)
83  #define SUN6I_LEAP_GET_VALUE(x)			(((x) & 0x00400000) >> 22)
84  
85  /*
86   * Get time values
87   */
88  #define SUN6I_TIME_GET_SEC_VALUE(x)		((x)  & 0x0000003f)
89  #define SUN6I_TIME_GET_MIN_VALUE(x)		(((x) & 0x00003f00) >> 8)
90  #define SUN6I_TIME_GET_HOUR_VALUE(x)		(((x) & 0x001f0000) >> 16)
91  
92  /*
93   * Set date values
94   */
95  #define SUN6I_DATE_SET_DAY_VALUE(x)		((x)       & 0x0000001f)
96  #define SUN6I_DATE_SET_MON_VALUE(x)		((x) <<  8 & 0x00000f00)
97  #define SUN6I_DATE_SET_YEAR_VALUE(x)		((x) << 16 & 0x003f0000)
98  #define SUN6I_LEAP_SET_VALUE(x)			((x) << 22 & 0x00400000)
99  
100  /*
101   * Set time values
102   */
103  #define SUN6I_TIME_SET_SEC_VALUE(x)		((x)       & 0x0000003f)
104  #define SUN6I_TIME_SET_MIN_VALUE(x)		((x) <<  8 & 0x00003f00)
105  #define SUN6I_TIME_SET_HOUR_VALUE(x)		((x) << 16 & 0x001f0000)
106  
107  /*
108   * The year parameter passed to the driver is usually an offset relative to
109   * the year 1900. This macro is used to convert this offset to another one
110   * relative to the minimum year allowed by the hardware.
111   *
112   * The year range is 1970 - 2033. This range is selected to match Allwinner's
113   * driver, even though it is somewhat limited.
114   */
115  #define SUN6I_YEAR_MIN				1970
116  #define SUN6I_YEAR_OFF				(SUN6I_YEAR_MIN - 1900)
117  
118  #define SECS_PER_DAY				(24 * 3600ULL)
119  
120  /*
121   * There are other differences between models, including:
122   *
123   *   - number of GPIO pins that can be configured to hold a certain level
124   *   - crypto-key related registers (H5, H6)
125   *   - boot process related (super standby, secondary processor entry address)
126   *     registers (R40, H6)
127   *   - SYS power domain controls (R40)
128   *   - DCXO controls (H6)
129   *   - RC oscillator calibration (H6)
130   *
131   * These functions are not covered by this driver.
132   */
133  struct sun6i_rtc_clk_data {
134  	unsigned long rc_osc_rate;
135  	unsigned int fixed_prescaler : 16;
136  	unsigned int has_prescaler : 1;
137  	unsigned int has_out_clk : 1;
138  	unsigned int has_losc_en : 1;
139  	unsigned int has_auto_swt : 1;
140  };
141  
142  #define RTC_LINEAR_DAY	BIT(0)
143  
144  struct sun6i_rtc_dev {
145  	struct rtc_device *rtc;
146  	const struct sun6i_rtc_clk_data *data;
147  	void __iomem *base;
148  	int irq;
149  	time64_t alarm;
150  	unsigned long flags;
151  
152  	struct clk_hw hw;
153  	struct clk_hw *int_osc;
154  	struct clk *losc;
155  	struct clk *ext_losc;
156  
157  	spinlock_t lock;
158  };
159  
160  static struct sun6i_rtc_dev *sun6i_rtc;
161  
sun6i_rtc_osc_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)162  static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
163  					       unsigned long parent_rate)
164  {
165  	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
166  	u32 val = 0;
167  
168  	val = readl(rtc->base + SUN6I_LOSC_CTRL);
169  	if (val & SUN6I_LOSC_CTRL_EXT_OSC)
170  		return parent_rate;
171  
172  	if (rtc->data->fixed_prescaler)
173  		parent_rate /= rtc->data->fixed_prescaler;
174  
175  	if (rtc->data->has_prescaler) {
176  		val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
177  		val &= GENMASK(4, 0);
178  	}
179  
180  	return parent_rate / (val + 1);
181  }
182  
sun6i_rtc_osc_get_parent(struct clk_hw * hw)183  static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
184  {
185  	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
186  
187  	return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
188  }
189  
sun6i_rtc_osc_set_parent(struct clk_hw * hw,u8 index)190  static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
191  {
192  	struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
193  	unsigned long flags;
194  	u32 val;
195  
196  	if (index > 1)
197  		return -EINVAL;
198  
199  	spin_lock_irqsave(&rtc->lock, flags);
200  	val = readl(rtc->base + SUN6I_LOSC_CTRL);
201  	val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
202  	val |= SUN6I_LOSC_CTRL_KEY;
203  	val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
204  	if (rtc->data->has_losc_en) {
205  		val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
206  		val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
207  	}
208  	writel(val, rtc->base + SUN6I_LOSC_CTRL);
209  	spin_unlock_irqrestore(&rtc->lock, flags);
210  
211  	return 0;
212  }
213  
214  static const struct clk_ops sun6i_rtc_osc_ops = {
215  	.recalc_rate	= sun6i_rtc_osc_recalc_rate,
216  	.determine_rate	= clk_hw_determine_rate_no_reparent,
217  
218  	.get_parent	= sun6i_rtc_osc_get_parent,
219  	.set_parent	= sun6i_rtc_osc_set_parent,
220  };
221  
sun6i_rtc_clk_init(struct device_node * node,const struct sun6i_rtc_clk_data * data)222  static void __init sun6i_rtc_clk_init(struct device_node *node,
223  				      const struct sun6i_rtc_clk_data *data)
224  {
225  	struct clk_hw_onecell_data *clk_data;
226  	struct sun6i_rtc_dev *rtc;
227  	struct clk_init_data init = {
228  		.ops		= &sun6i_rtc_osc_ops,
229  		.name		= "losc",
230  	};
231  	const char *iosc_name = "rtc-int-osc";
232  	const char *clkout_name = "osc32k-out";
233  	const char *parents[2];
234  	u32 reg;
235  
236  	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
237  	if (!rtc)
238  		return;
239  
240  	rtc->data = data;
241  	clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
242  	if (!clk_data) {
243  		kfree(rtc);
244  		return;
245  	}
246  
247  	spin_lock_init(&rtc->lock);
248  
249  	rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
250  	if (IS_ERR(rtc->base)) {
251  		pr_crit("Can't map RTC registers");
252  		goto err;
253  	}
254  
255  	reg = SUN6I_LOSC_CTRL_KEY;
256  	if (rtc->data->has_auto_swt) {
257  		/* Bypass auto-switch to int osc, on ext losc failure */
258  		reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
259  		writel(reg, rtc->base + SUN6I_LOSC_CTRL);
260  	}
261  
262  	/* Switch to the external, more precise, oscillator, if present */
263  	if (of_property_present(node, "clocks")) {
264  		reg |= SUN6I_LOSC_CTRL_EXT_OSC;
265  		if (rtc->data->has_losc_en)
266  			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
267  	}
268  	writel(reg, rtc->base + SUN6I_LOSC_CTRL);
269  
270  	/* Yes, I know, this is ugly. */
271  	sun6i_rtc = rtc;
272  
273  	of_property_read_string_index(node, "clock-output-names", 2,
274  				      &iosc_name);
275  
276  	rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
277  								iosc_name,
278  								NULL, 0,
279  								rtc->data->rc_osc_rate,
280  								300000000);
281  	if (IS_ERR(rtc->int_osc)) {
282  		pr_crit("Couldn't register the internal oscillator\n");
283  		goto err;
284  	}
285  
286  	parents[0] = clk_hw_get_name(rtc->int_osc);
287  	/* If there is no external oscillator, this will be NULL and ... */
288  	parents[1] = of_clk_get_parent_name(node, 0);
289  
290  	rtc->hw.init = &init;
291  
292  	init.parent_names = parents;
293  	/* ... number of clock parents will be 1. */
294  	init.num_parents = of_clk_get_parent_count(node) + 1;
295  	of_property_read_string_index(node, "clock-output-names", 0,
296  				      &init.name);
297  
298  	rtc->losc = clk_register(NULL, &rtc->hw);
299  	if (IS_ERR(rtc->losc)) {
300  		pr_crit("Couldn't register the LOSC clock\n");
301  		goto err_register;
302  	}
303  
304  	of_property_read_string_index(node, "clock-output-names", 1,
305  				      &clkout_name);
306  	rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
307  					  0, rtc->base + SUN6I_LOSC_OUT_GATING,
308  					  SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
309  					  &rtc->lock);
310  	if (IS_ERR(rtc->ext_losc)) {
311  		pr_crit("Couldn't register the LOSC external gate\n");
312  		goto err_register;
313  	}
314  
315  	clk_data->num = 3;
316  	clk_data->hws[0] = &rtc->hw;
317  	clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
318  	clk_data->hws[2] = rtc->int_osc;
319  	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
320  	return;
321  
322  err_register:
323  	clk_hw_unregister_fixed_rate(rtc->int_osc);
324  err:
325  	kfree(clk_data);
326  }
327  
328  static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
329  	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
330  	.has_prescaler = 1,
331  };
332  
sun6i_a31_rtc_clk_init(struct device_node * node)333  static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
334  {
335  	sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
336  }
337  CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
338  		      sun6i_a31_rtc_clk_init);
339  
340  static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
341  	.rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
342  	.has_prescaler = 1,
343  	.has_out_clk = 1,
344  };
345  
sun8i_a23_rtc_clk_init(struct device_node * node)346  static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
347  {
348  	sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
349  }
350  CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
351  		      sun8i_a23_rtc_clk_init);
352  
353  static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
354  	.rc_osc_rate = 16000000,
355  	.fixed_prescaler = 32,
356  	.has_prescaler = 1,
357  	.has_out_clk = 1,
358  };
359  
sun8i_h3_rtc_clk_init(struct device_node * node)360  static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
361  {
362  	sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
363  }
364  CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
365  		      sun8i_h3_rtc_clk_init);
366  /* As far as we are concerned, clocks for H5 are the same as H3 */
367  CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
368  		      sun8i_h3_rtc_clk_init);
369  
370  static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
371  	.rc_osc_rate = 16000000,
372  	.fixed_prescaler = 32,
373  	.has_prescaler = 1,
374  	.has_out_clk = 1,
375  	.has_losc_en = 1,
376  	.has_auto_swt = 1,
377  };
378  
sun50i_h6_rtc_clk_init(struct device_node * node)379  static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
380  {
381  	sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
382  }
383  CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
384  		      sun50i_h6_rtc_clk_init);
385  
386  /*
387   * The R40 user manual is self-conflicting on whether the prescaler is
388   * fixed or configurable. The clock diagram shows it as fixed, but there
389   * is also a configurable divider in the RTC block.
390   */
391  static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
392  	.rc_osc_rate = 16000000,
393  	.fixed_prescaler = 512,
394  };
sun8i_r40_rtc_clk_init(struct device_node * node)395  static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
396  {
397  	sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
398  }
399  CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
400  		      sun8i_r40_rtc_clk_init);
401  
402  static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
403  	.rc_osc_rate = 32000,
404  	.has_out_clk = 1,
405  	.has_auto_swt = 1,
406  };
407  
sun8i_v3_rtc_clk_init(struct device_node * node)408  static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
409  {
410  	sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
411  }
412  CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
413  		      sun8i_v3_rtc_clk_init);
414  
sun6i_rtc_alarmirq(int irq,void * id)415  static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
416  {
417  	struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
418  	irqreturn_t ret = IRQ_NONE;
419  	u32 val;
420  
421  	spin_lock(&chip->lock);
422  	val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
423  
424  	if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
425  		val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
426  		writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
427  
428  		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
429  
430  		ret = IRQ_HANDLED;
431  	}
432  	spin_unlock(&chip->lock);
433  
434  	return ret;
435  }
436  
sun6i_rtc_setaie(int to,struct sun6i_rtc_dev * chip)437  static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
438  {
439  	u32 alrm_val = 0;
440  	u32 alrm_irq_val = 0;
441  	u32 alrm_wake_val = 0;
442  	unsigned long flags;
443  
444  	if (to) {
445  		alrm_val = SUN6I_ALRM_EN_CNT_EN;
446  		alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
447  		alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
448  	} else {
449  		writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
450  		       chip->base + SUN6I_ALRM_IRQ_STA);
451  	}
452  
453  	spin_lock_irqsave(&chip->lock, flags);
454  	writel(alrm_val, chip->base + SUN6I_ALRM_EN);
455  	writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
456  	writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
457  	spin_unlock_irqrestore(&chip->lock, flags);
458  }
459  
sun6i_rtc_gettime(struct device * dev,struct rtc_time * rtc_tm)460  static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
461  {
462  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
463  	u32 date, time;
464  
465  	/*
466  	 * read again in case it changes
467  	 */
468  	do {
469  		date = readl(chip->base + SUN6I_RTC_YMD);
470  		time = readl(chip->base + SUN6I_RTC_HMS);
471  	} while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
472  		 (time != readl(chip->base + SUN6I_RTC_HMS)));
473  
474  	if (chip->flags & RTC_LINEAR_DAY) {
475  		/*
476  		 * Newer chips store a linear day number, the manual
477  		 * does not mandate any epoch base. The BSP driver uses
478  		 * the UNIX epoch, let's just copy that, as it's the
479  		 * easiest anyway.
480  		 */
481  		rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm);
482  	} else {
483  		rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
484  		rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date) - 1;
485  		rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
486  
487  		/*
488  		 * switch from (data_year->min)-relative offset to
489  		 * a (1900)-relative one
490  		 */
491  		rtc_tm->tm_year += SUN6I_YEAR_OFF;
492  	}
493  
494  	rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);
495  	rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);
496  	rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
497  
498  	return 0;
499  }
500  
sun6i_rtc_getalarm(struct device * dev,struct rtc_wkalrm * wkalrm)501  static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
502  {
503  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
504  	unsigned long flags;
505  	u32 alrm_st;
506  	u32 alrm_en;
507  
508  	spin_lock_irqsave(&chip->lock, flags);
509  	alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
510  	alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
511  	spin_unlock_irqrestore(&chip->lock, flags);
512  
513  	wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
514  	wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
515  	rtc_time64_to_tm(chip->alarm, &wkalrm->time);
516  
517  	return 0;
518  }
519  
sun6i_rtc_setalarm(struct device * dev,struct rtc_wkalrm * wkalrm)520  static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
521  {
522  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
523  	struct rtc_time *alrm_tm = &wkalrm->time;
524  	struct rtc_time tm_now;
525  	time64_t time_set;
526  	u32 counter_val, counter_val_hms;
527  	int ret;
528  
529  	time_set = rtc_tm_to_time64(alrm_tm);
530  
531  	if (chip->flags & RTC_LINEAR_DAY) {
532  		/*
533  		 * The alarm registers hold the actual alarm time, encoded
534  		 * in the same way (linear day + HMS) as the current time.
535  		 */
536  		counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec)  |
537  				  SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min)  |
538  				  SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour);
539  		/* The division will cut off the H:M:S part of alrm_tm. */
540  		counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY);
541  	} else {
542  		/* The alarm register holds the number of seconds left. */
543  		time64_t time_now;
544  
545  		ret = sun6i_rtc_gettime(dev, &tm_now);
546  		if (ret < 0) {
547  			dev_err(dev, "Error in getting time\n");
548  			return -EINVAL;
549  		}
550  
551  		time_now = rtc_tm_to_time64(&tm_now);
552  		if (time_set <= time_now) {
553  			dev_err(dev, "Date to set in the past\n");
554  			return -EINVAL;
555  		}
556  		if ((time_set - time_now) > U32_MAX) {
557  			dev_err(dev, "Date too far in the future\n");
558  			return -EINVAL;
559  		}
560  
561  		counter_val = time_set - time_now;
562  	}
563  
564  	sun6i_rtc_setaie(0, chip);
565  	writel(0, chip->base + SUN6I_ALRM_COUNTER);
566  	if (chip->flags & RTC_LINEAR_DAY)
567  		writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS);
568  	usleep_range(100, 300);
569  
570  	writel(counter_val, chip->base + SUN6I_ALRM_COUNTER);
571  	if (chip->flags & RTC_LINEAR_DAY)
572  		writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS);
573  	chip->alarm = time_set;
574  
575  	sun6i_rtc_setaie(wkalrm->enabled, chip);
576  
577  	return 0;
578  }
579  
sun6i_rtc_wait(struct sun6i_rtc_dev * chip,int offset,unsigned int mask,unsigned int ms_timeout)580  static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
581  			  unsigned int mask, unsigned int ms_timeout)
582  {
583  	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
584  	u32 reg;
585  
586  	do {
587  		reg = readl(chip->base + offset);
588  		reg &= mask;
589  
590  		if (!reg)
591  			return 0;
592  
593  	} while (time_before(jiffies, timeout));
594  
595  	return -ETIMEDOUT;
596  }
597  
sun6i_rtc_settime(struct device * dev,struct rtc_time * rtc_tm)598  static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
599  {
600  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
601  	u32 date = 0;
602  	u32 time = 0;
603  
604  	time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
605  		SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
606  		SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
607  
608  	if (chip->flags & RTC_LINEAR_DAY) {
609  		/* The division will cut off the H:M:S part of rtc_tm. */
610  		date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY);
611  	} else {
612  		rtc_tm->tm_year -= SUN6I_YEAR_OFF;
613  		rtc_tm->tm_mon += 1;
614  
615  		date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
616  			SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
617  			SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
618  
619  		if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
620  			date |= SUN6I_LEAP_SET_VALUE(1);
621  	}
622  
623  	/* Check whether registers are writable */
624  	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
625  			   SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
626  		dev_err(dev, "rtc is still busy.\n");
627  		return -EBUSY;
628  	}
629  
630  	writel(time, chip->base + SUN6I_RTC_HMS);
631  
632  	/*
633  	 * After writing the RTC HH-MM-SS register, the
634  	 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
635  	 * be cleared until the real writing operation is finished
636  	 */
637  
638  	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
639  			   SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
640  		dev_err(dev, "Failed to set rtc time.\n");
641  		return -ETIMEDOUT;
642  	}
643  
644  	writel(date, chip->base + SUN6I_RTC_YMD);
645  
646  	/*
647  	 * After writing the RTC YY-MM-DD register, the
648  	 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
649  	 * be cleared until the real writing operation is finished
650  	 */
651  
652  	if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
653  			   SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
654  		dev_err(dev, "Failed to set rtc time.\n");
655  		return -ETIMEDOUT;
656  	}
657  
658  	return 0;
659  }
660  
sun6i_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)661  static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
662  {
663  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
664  
665  	if (!enabled)
666  		sun6i_rtc_setaie(enabled, chip);
667  
668  	return 0;
669  }
670  
671  static const struct rtc_class_ops sun6i_rtc_ops = {
672  	.read_time		= sun6i_rtc_gettime,
673  	.set_time		= sun6i_rtc_settime,
674  	.read_alarm		= sun6i_rtc_getalarm,
675  	.set_alarm		= sun6i_rtc_setalarm,
676  	.alarm_irq_enable	= sun6i_rtc_alarm_irq_enable
677  };
678  
sun6i_rtc_nvmem_read(void * priv,unsigned int offset,void * _val,size_t bytes)679  static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes)
680  {
681  	struct sun6i_rtc_dev *chip = priv;
682  	u32 *val = _val;
683  	int i;
684  
685  	for (i = 0; i < bytes / 4; ++i)
686  		val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i);
687  
688  	return 0;
689  }
690  
sun6i_rtc_nvmem_write(void * priv,unsigned int offset,void * _val,size_t bytes)691  static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes)
692  {
693  	struct sun6i_rtc_dev *chip = priv;
694  	u32 *val = _val;
695  	int i;
696  
697  	for (i = 0; i < bytes / 4; ++i)
698  		writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i);
699  
700  	return 0;
701  }
702  
703  static struct nvmem_config sun6i_rtc_nvmem_cfg = {
704  	.type		= NVMEM_TYPE_BATTERY_BACKED,
705  	.reg_read	= sun6i_rtc_nvmem_read,
706  	.reg_write	= sun6i_rtc_nvmem_write,
707  	.size		= SUN6I_GP_DATA_SIZE,
708  	.word_size	= 4,
709  	.stride		= 4,
710  };
711  
712  #ifdef CONFIG_PM_SLEEP
713  /* Enable IRQ wake on suspend, to wake up from RTC. */
sun6i_rtc_suspend(struct device * dev)714  static int sun6i_rtc_suspend(struct device *dev)
715  {
716  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
717  
718  	if (device_may_wakeup(dev))
719  		enable_irq_wake(chip->irq);
720  
721  	return 0;
722  }
723  
724  /* Disable IRQ wake on resume. */
sun6i_rtc_resume(struct device * dev)725  static int sun6i_rtc_resume(struct device *dev)
726  {
727  	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
728  
729  	if (device_may_wakeup(dev))
730  		disable_irq_wake(chip->irq);
731  
732  	return 0;
733  }
734  #endif
735  
736  static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
737  	sun6i_rtc_suspend, sun6i_rtc_resume);
738  
sun6i_rtc_bus_clk_cleanup(void * data)739  static void sun6i_rtc_bus_clk_cleanup(void *data)
740  {
741  	struct clk *bus_clk = data;
742  
743  	clk_disable_unprepare(bus_clk);
744  }
745  
sun6i_rtc_probe(struct platform_device * pdev)746  static int sun6i_rtc_probe(struct platform_device *pdev)
747  {
748  	struct sun6i_rtc_dev *chip = sun6i_rtc;
749  	struct device *dev = &pdev->dev;
750  	struct clk *bus_clk;
751  	int ret;
752  
753  	bus_clk = devm_clk_get_optional(dev, "bus");
754  	if (IS_ERR(bus_clk))
755  		return PTR_ERR(bus_clk);
756  
757  	if (bus_clk) {
758  		ret = clk_prepare_enable(bus_clk);
759  		if (ret)
760  			return ret;
761  
762  		ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup,
763  					       bus_clk);
764  		if (ret)
765  			return ret;
766  	}
767  
768  	if (!chip) {
769  		chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
770  		if (!chip)
771  			return -ENOMEM;
772  
773  		spin_lock_init(&chip->lock);
774  
775  		chip->base = devm_platform_ioremap_resource(pdev, 0);
776  		if (IS_ERR(chip->base))
777  			return PTR_ERR(chip->base);
778  
779  		if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) {
780  			ret = sun6i_rtc_ccu_probe(dev, chip->base);
781  			if (ret)
782  				return ret;
783  		}
784  	}
785  
786  	platform_set_drvdata(pdev, chip);
787  
788  	chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev);
789  
790  	chip->irq = platform_get_irq(pdev, 0);
791  	if (chip->irq < 0)
792  		return chip->irq;
793  
794  	ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
795  			       0, dev_name(&pdev->dev), chip);
796  	if (ret) {
797  		dev_err(&pdev->dev, "Could not request IRQ\n");
798  		return ret;
799  	}
800  
801  	/* clear the alarm counter value */
802  	writel(0, chip->base + SUN6I_ALRM_COUNTER);
803  
804  	/* disable counter alarm */
805  	writel(0, chip->base + SUN6I_ALRM_EN);
806  
807  	/* disable counter alarm interrupt */
808  	writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
809  
810  	/* disable week alarm */
811  	writel(0, chip->base + SUN6I_ALRM1_EN);
812  
813  	/* disable week alarm interrupt */
814  	writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
815  
816  	/* clear counter alarm pending interrupts */
817  	writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
818  	       chip->base + SUN6I_ALRM_IRQ_STA);
819  
820  	/* clear week alarm pending interrupts */
821  	writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
822  	       chip->base + SUN6I_ALRM1_IRQ_STA);
823  
824  	/* disable alarm wakeup */
825  	writel(0, chip->base + SUN6I_ALARM_CONFIG);
826  
827  	clk_prepare_enable(chip->losc);
828  
829  	device_init_wakeup(&pdev->dev, 1);
830  
831  	chip->rtc = devm_rtc_allocate_device(&pdev->dev);
832  	if (IS_ERR(chip->rtc))
833  		return PTR_ERR(chip->rtc);
834  
835  	chip->rtc->ops = &sun6i_rtc_ops;
836  	if (chip->flags & RTC_LINEAR_DAY)
837  		chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1;
838  	else
839  		chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
840  
841  	ret = devm_rtc_register_device(chip->rtc);
842  	if (ret)
843  		return ret;
844  
845  	sun6i_rtc_nvmem_cfg.priv = chip;
846  	ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg);
847  	if (ret)
848  		return ret;
849  
850  	return 0;
851  }
852  
853  /*
854   * As far as RTC functionality goes, all models are the same. The
855   * datasheets claim that different models have different number of
856   * registers available for non-volatile storage, but experiments show
857   * that all SoCs have 16 registers available for this purpose.
858   */
859  static const struct of_device_id sun6i_rtc_dt_ids[] = {
860  	{ .compatible = "allwinner,sun6i-a31-rtc" },
861  	{ .compatible = "allwinner,sun8i-a23-rtc" },
862  	{ .compatible = "allwinner,sun8i-h3-rtc" },
863  	{ .compatible = "allwinner,sun8i-r40-rtc" },
864  	{ .compatible = "allwinner,sun8i-v3-rtc" },
865  	{ .compatible = "allwinner,sun50i-h5-rtc" },
866  	{ .compatible = "allwinner,sun50i-h6-rtc" },
867  	{ .compatible = "allwinner,sun50i-h616-rtc",
868  		.data = (void *)RTC_LINEAR_DAY },
869  	{ .compatible = "allwinner,sun50i-r329-rtc",
870  		.data = (void *)RTC_LINEAR_DAY },
871  	{ /* sentinel */ },
872  };
873  MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
874  
875  static struct platform_driver sun6i_rtc_driver = {
876  	.probe		= sun6i_rtc_probe,
877  	.driver		= {
878  		.name		= "sun6i-rtc",
879  		.of_match_table = sun6i_rtc_dt_ids,
880  		.pm = &sun6i_rtc_pm_ops,
881  	},
882  };
883  builtin_platform_driver(sun6i_rtc_driver);
884