1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/acpi.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 
11 #include "pinctrl-msm.h"
12 
13 #define NORTH	0x00500000
14 #define SOUTH	0x00900000
15 #define EAST	0x00100000
16 #define REG_SIZE 0x1000
17 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)	\
18 	{						\
19 		.grp = PINCTRL_PINGROUP("gpio" #id, 	\
20 			gpio##id##_pins, 		\
21 			ARRAY_SIZE(gpio##id##_pins)),	\
22 		.funcs = (int[]){			\
23 			msm_mux_gpio, /* gpio mode */	\
24 			msm_mux_##f1,			\
25 			msm_mux_##f2,			\
26 			msm_mux_##f3,			\
27 			msm_mux_##f4,			\
28 			msm_mux_##f5,			\
29 			msm_mux_##f6,			\
30 			msm_mux_##f7,			\
31 			msm_mux_##f8,			\
32 			msm_mux_##f9,			\
33 			msm_mux_##f10			\
34 		},					\
35 		.nfuncs = 11,				\
36 		.ctl_reg = base + REG_SIZE * id,		\
37 		.io_reg = base + 0x4 + REG_SIZE * id,		\
38 		.intr_cfg_reg = base + 0x8 + REG_SIZE * id,	\
39 		.intr_status_reg = base + 0xc + REG_SIZE * id,	\
40 		.intr_target_reg = base + 0x8 + REG_SIZE * id,	\
41 		.mux_bit = 2,			\
42 		.pull_bit = 0,			\
43 		.drv_bit = 6,			\
44 		.oe_bit = 9,			\
45 		.in_bit = 0,			\
46 		.out_bit = 1,			\
47 		.intr_enable_bit = 0,		\
48 		.intr_status_bit = 0,		\
49 		.intr_target_bit = 5,		\
50 		.intr_target_kpss_val = 3,	\
51 		.intr_raw_status_bit = 4,	\
52 		.intr_polarity_bit = 1,		\
53 		.intr_detection_bit = 2,	\
54 		.intr_detection_width = 2,	\
55 	}
56 
57 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)	\
58 	{						\
59 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
60 			pg_name##_pins, 		\
61 			ARRAY_SIZE(pg_name##_pins)),	\
62 		.ctl_reg = ctl,				\
63 		.io_reg = 0,				\
64 		.intr_cfg_reg = 0,			\
65 		.intr_status_reg = 0,			\
66 		.intr_target_reg = 0,			\
67 		.mux_bit = -1,				\
68 		.pull_bit = pull,			\
69 		.drv_bit = drv,				\
70 		.oe_bit = -1,				\
71 		.in_bit = -1,				\
72 		.out_bit = -1,				\
73 		.intr_enable_bit = -1,			\
74 		.intr_status_bit = -1,			\
75 		.intr_target_bit = -1,			\
76 		.intr_raw_status_bit = -1,		\
77 		.intr_polarity_bit = -1,		\
78 		.intr_detection_bit = -1,		\
79 		.intr_detection_width = -1,		\
80 	}
81 
82 #define UFS_RESET(pg_name, offset)				\
83 	{						\
84 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
85 			pg_name##_pins, 		\
86 			ARRAY_SIZE(pg_name##_pins)),	\
87 		.ctl_reg = offset,			\
88 		.io_reg = offset + 0x4,			\
89 		.intr_cfg_reg = 0,			\
90 		.intr_status_reg = 0,			\
91 		.intr_target_reg = 0,			\
92 		.mux_bit = -1,				\
93 		.pull_bit = 3,				\
94 		.drv_bit = 0,				\
95 		.oe_bit = -1,				\
96 		.in_bit = -1,				\
97 		.out_bit = 0,				\
98 		.intr_enable_bit = -1,			\
99 		.intr_status_bit = -1,			\
100 		.intr_target_bit = -1,			\
101 		.intr_raw_status_bit = -1,		\
102 		.intr_polarity_bit = -1,		\
103 		.intr_detection_bit = -1,		\
104 		.intr_detection_width = -1,		\
105 	}
106 static const struct pinctrl_pin_desc sdm845_pins[] = {
107 	PINCTRL_PIN(0, "GPIO_0"),
108 	PINCTRL_PIN(1, "GPIO_1"),
109 	PINCTRL_PIN(2, "GPIO_2"),
110 	PINCTRL_PIN(3, "GPIO_3"),
111 	PINCTRL_PIN(4, "GPIO_4"),
112 	PINCTRL_PIN(5, "GPIO_5"),
113 	PINCTRL_PIN(6, "GPIO_6"),
114 	PINCTRL_PIN(7, "GPIO_7"),
115 	PINCTRL_PIN(8, "GPIO_8"),
116 	PINCTRL_PIN(9, "GPIO_9"),
117 	PINCTRL_PIN(10, "GPIO_10"),
118 	PINCTRL_PIN(11, "GPIO_11"),
119 	PINCTRL_PIN(12, "GPIO_12"),
120 	PINCTRL_PIN(13, "GPIO_13"),
121 	PINCTRL_PIN(14, "GPIO_14"),
122 	PINCTRL_PIN(15, "GPIO_15"),
123 	PINCTRL_PIN(16, "GPIO_16"),
124 	PINCTRL_PIN(17, "GPIO_17"),
125 	PINCTRL_PIN(18, "GPIO_18"),
126 	PINCTRL_PIN(19, "GPIO_19"),
127 	PINCTRL_PIN(20, "GPIO_20"),
128 	PINCTRL_PIN(21, "GPIO_21"),
129 	PINCTRL_PIN(22, "GPIO_22"),
130 	PINCTRL_PIN(23, "GPIO_23"),
131 	PINCTRL_PIN(24, "GPIO_24"),
132 	PINCTRL_PIN(25, "GPIO_25"),
133 	PINCTRL_PIN(26, "GPIO_26"),
134 	PINCTRL_PIN(27, "GPIO_27"),
135 	PINCTRL_PIN(28, "GPIO_28"),
136 	PINCTRL_PIN(29, "GPIO_29"),
137 	PINCTRL_PIN(30, "GPIO_30"),
138 	PINCTRL_PIN(31, "GPIO_31"),
139 	PINCTRL_PIN(32, "GPIO_32"),
140 	PINCTRL_PIN(33, "GPIO_33"),
141 	PINCTRL_PIN(34, "GPIO_34"),
142 	PINCTRL_PIN(35, "GPIO_35"),
143 	PINCTRL_PIN(36, "GPIO_36"),
144 	PINCTRL_PIN(37, "GPIO_37"),
145 	PINCTRL_PIN(38, "GPIO_38"),
146 	PINCTRL_PIN(39, "GPIO_39"),
147 	PINCTRL_PIN(40, "GPIO_40"),
148 	PINCTRL_PIN(41, "GPIO_41"),
149 	PINCTRL_PIN(42, "GPIO_42"),
150 	PINCTRL_PIN(43, "GPIO_43"),
151 	PINCTRL_PIN(44, "GPIO_44"),
152 	PINCTRL_PIN(45, "GPIO_45"),
153 	PINCTRL_PIN(46, "GPIO_46"),
154 	PINCTRL_PIN(47, "GPIO_47"),
155 	PINCTRL_PIN(48, "GPIO_48"),
156 	PINCTRL_PIN(49, "GPIO_49"),
157 	PINCTRL_PIN(50, "GPIO_50"),
158 	PINCTRL_PIN(51, "GPIO_51"),
159 	PINCTRL_PIN(52, "GPIO_52"),
160 	PINCTRL_PIN(53, "GPIO_53"),
161 	PINCTRL_PIN(54, "GPIO_54"),
162 	PINCTRL_PIN(55, "GPIO_55"),
163 	PINCTRL_PIN(56, "GPIO_56"),
164 	PINCTRL_PIN(57, "GPIO_57"),
165 	PINCTRL_PIN(58, "GPIO_58"),
166 	PINCTRL_PIN(59, "GPIO_59"),
167 	PINCTRL_PIN(60, "GPIO_60"),
168 	PINCTRL_PIN(61, "GPIO_61"),
169 	PINCTRL_PIN(62, "GPIO_62"),
170 	PINCTRL_PIN(63, "GPIO_63"),
171 	PINCTRL_PIN(64, "GPIO_64"),
172 	PINCTRL_PIN(65, "GPIO_65"),
173 	PINCTRL_PIN(66, "GPIO_66"),
174 	PINCTRL_PIN(67, "GPIO_67"),
175 	PINCTRL_PIN(68, "GPIO_68"),
176 	PINCTRL_PIN(69, "GPIO_69"),
177 	PINCTRL_PIN(70, "GPIO_70"),
178 	PINCTRL_PIN(71, "GPIO_71"),
179 	PINCTRL_PIN(72, "GPIO_72"),
180 	PINCTRL_PIN(73, "GPIO_73"),
181 	PINCTRL_PIN(74, "GPIO_74"),
182 	PINCTRL_PIN(75, "GPIO_75"),
183 	PINCTRL_PIN(76, "GPIO_76"),
184 	PINCTRL_PIN(77, "GPIO_77"),
185 	PINCTRL_PIN(78, "GPIO_78"),
186 	PINCTRL_PIN(79, "GPIO_79"),
187 	PINCTRL_PIN(80, "GPIO_80"),
188 	PINCTRL_PIN(81, "GPIO_81"),
189 	PINCTRL_PIN(82, "GPIO_82"),
190 	PINCTRL_PIN(83, "GPIO_83"),
191 	PINCTRL_PIN(84, "GPIO_84"),
192 	PINCTRL_PIN(85, "GPIO_85"),
193 	PINCTRL_PIN(86, "GPIO_86"),
194 	PINCTRL_PIN(87, "GPIO_87"),
195 	PINCTRL_PIN(88, "GPIO_88"),
196 	PINCTRL_PIN(89, "GPIO_89"),
197 	PINCTRL_PIN(90, "GPIO_90"),
198 	PINCTRL_PIN(91, "GPIO_91"),
199 	PINCTRL_PIN(92, "GPIO_92"),
200 	PINCTRL_PIN(93, "GPIO_93"),
201 	PINCTRL_PIN(94, "GPIO_94"),
202 	PINCTRL_PIN(95, "GPIO_95"),
203 	PINCTRL_PIN(96, "GPIO_96"),
204 	PINCTRL_PIN(97, "GPIO_97"),
205 	PINCTRL_PIN(98, "GPIO_98"),
206 	PINCTRL_PIN(99, "GPIO_99"),
207 	PINCTRL_PIN(100, "GPIO_100"),
208 	PINCTRL_PIN(101, "GPIO_101"),
209 	PINCTRL_PIN(102, "GPIO_102"),
210 	PINCTRL_PIN(103, "GPIO_103"),
211 	PINCTRL_PIN(104, "GPIO_104"),
212 	PINCTRL_PIN(105, "GPIO_105"),
213 	PINCTRL_PIN(106, "GPIO_106"),
214 	PINCTRL_PIN(107, "GPIO_107"),
215 	PINCTRL_PIN(108, "GPIO_108"),
216 	PINCTRL_PIN(109, "GPIO_109"),
217 	PINCTRL_PIN(110, "GPIO_110"),
218 	PINCTRL_PIN(111, "GPIO_111"),
219 	PINCTRL_PIN(112, "GPIO_112"),
220 	PINCTRL_PIN(113, "GPIO_113"),
221 	PINCTRL_PIN(114, "GPIO_114"),
222 	PINCTRL_PIN(115, "GPIO_115"),
223 	PINCTRL_PIN(116, "GPIO_116"),
224 	PINCTRL_PIN(117, "GPIO_117"),
225 	PINCTRL_PIN(118, "GPIO_118"),
226 	PINCTRL_PIN(119, "GPIO_119"),
227 	PINCTRL_PIN(120, "GPIO_120"),
228 	PINCTRL_PIN(121, "GPIO_121"),
229 	PINCTRL_PIN(122, "GPIO_122"),
230 	PINCTRL_PIN(123, "GPIO_123"),
231 	PINCTRL_PIN(124, "GPIO_124"),
232 	PINCTRL_PIN(125, "GPIO_125"),
233 	PINCTRL_PIN(126, "GPIO_126"),
234 	PINCTRL_PIN(127, "GPIO_127"),
235 	PINCTRL_PIN(128, "GPIO_128"),
236 	PINCTRL_PIN(129, "GPIO_129"),
237 	PINCTRL_PIN(130, "GPIO_130"),
238 	PINCTRL_PIN(131, "GPIO_131"),
239 	PINCTRL_PIN(132, "GPIO_132"),
240 	PINCTRL_PIN(133, "GPIO_133"),
241 	PINCTRL_PIN(134, "GPIO_134"),
242 	PINCTRL_PIN(135, "GPIO_135"),
243 	PINCTRL_PIN(136, "GPIO_136"),
244 	PINCTRL_PIN(137, "GPIO_137"),
245 	PINCTRL_PIN(138, "GPIO_138"),
246 	PINCTRL_PIN(139, "GPIO_139"),
247 	PINCTRL_PIN(140, "GPIO_140"),
248 	PINCTRL_PIN(141, "GPIO_141"),
249 	PINCTRL_PIN(142, "GPIO_142"),
250 	PINCTRL_PIN(143, "GPIO_143"),
251 	PINCTRL_PIN(144, "GPIO_144"),
252 	PINCTRL_PIN(145, "GPIO_145"),
253 	PINCTRL_PIN(146, "GPIO_146"),
254 	PINCTRL_PIN(147, "GPIO_147"),
255 	PINCTRL_PIN(148, "GPIO_148"),
256 	PINCTRL_PIN(149, "GPIO_149"),
257 	PINCTRL_PIN(150, "UFS_RESET"),
258 	PINCTRL_PIN(151, "SDC2_CLK"),
259 	PINCTRL_PIN(152, "SDC2_CMD"),
260 	PINCTRL_PIN(153, "SDC2_DATA"),
261 };
262 
263 #define DECLARE_MSM_GPIO_PINS(pin) \
264 	static const unsigned int gpio##pin##_pins[] = { pin }
265 DECLARE_MSM_GPIO_PINS(0);
266 DECLARE_MSM_GPIO_PINS(1);
267 DECLARE_MSM_GPIO_PINS(2);
268 DECLARE_MSM_GPIO_PINS(3);
269 DECLARE_MSM_GPIO_PINS(4);
270 DECLARE_MSM_GPIO_PINS(5);
271 DECLARE_MSM_GPIO_PINS(6);
272 DECLARE_MSM_GPIO_PINS(7);
273 DECLARE_MSM_GPIO_PINS(8);
274 DECLARE_MSM_GPIO_PINS(9);
275 DECLARE_MSM_GPIO_PINS(10);
276 DECLARE_MSM_GPIO_PINS(11);
277 DECLARE_MSM_GPIO_PINS(12);
278 DECLARE_MSM_GPIO_PINS(13);
279 DECLARE_MSM_GPIO_PINS(14);
280 DECLARE_MSM_GPIO_PINS(15);
281 DECLARE_MSM_GPIO_PINS(16);
282 DECLARE_MSM_GPIO_PINS(17);
283 DECLARE_MSM_GPIO_PINS(18);
284 DECLARE_MSM_GPIO_PINS(19);
285 DECLARE_MSM_GPIO_PINS(20);
286 DECLARE_MSM_GPIO_PINS(21);
287 DECLARE_MSM_GPIO_PINS(22);
288 DECLARE_MSM_GPIO_PINS(23);
289 DECLARE_MSM_GPIO_PINS(24);
290 DECLARE_MSM_GPIO_PINS(25);
291 DECLARE_MSM_GPIO_PINS(26);
292 DECLARE_MSM_GPIO_PINS(27);
293 DECLARE_MSM_GPIO_PINS(28);
294 DECLARE_MSM_GPIO_PINS(29);
295 DECLARE_MSM_GPIO_PINS(30);
296 DECLARE_MSM_GPIO_PINS(31);
297 DECLARE_MSM_GPIO_PINS(32);
298 DECLARE_MSM_GPIO_PINS(33);
299 DECLARE_MSM_GPIO_PINS(34);
300 DECLARE_MSM_GPIO_PINS(35);
301 DECLARE_MSM_GPIO_PINS(36);
302 DECLARE_MSM_GPIO_PINS(37);
303 DECLARE_MSM_GPIO_PINS(38);
304 DECLARE_MSM_GPIO_PINS(39);
305 DECLARE_MSM_GPIO_PINS(40);
306 DECLARE_MSM_GPIO_PINS(41);
307 DECLARE_MSM_GPIO_PINS(42);
308 DECLARE_MSM_GPIO_PINS(43);
309 DECLARE_MSM_GPIO_PINS(44);
310 DECLARE_MSM_GPIO_PINS(45);
311 DECLARE_MSM_GPIO_PINS(46);
312 DECLARE_MSM_GPIO_PINS(47);
313 DECLARE_MSM_GPIO_PINS(48);
314 DECLARE_MSM_GPIO_PINS(49);
315 DECLARE_MSM_GPIO_PINS(50);
316 DECLARE_MSM_GPIO_PINS(51);
317 DECLARE_MSM_GPIO_PINS(52);
318 DECLARE_MSM_GPIO_PINS(53);
319 DECLARE_MSM_GPIO_PINS(54);
320 DECLARE_MSM_GPIO_PINS(55);
321 DECLARE_MSM_GPIO_PINS(56);
322 DECLARE_MSM_GPIO_PINS(57);
323 DECLARE_MSM_GPIO_PINS(58);
324 DECLARE_MSM_GPIO_PINS(59);
325 DECLARE_MSM_GPIO_PINS(60);
326 DECLARE_MSM_GPIO_PINS(61);
327 DECLARE_MSM_GPIO_PINS(62);
328 DECLARE_MSM_GPIO_PINS(63);
329 DECLARE_MSM_GPIO_PINS(64);
330 DECLARE_MSM_GPIO_PINS(65);
331 DECLARE_MSM_GPIO_PINS(66);
332 DECLARE_MSM_GPIO_PINS(67);
333 DECLARE_MSM_GPIO_PINS(68);
334 DECLARE_MSM_GPIO_PINS(69);
335 DECLARE_MSM_GPIO_PINS(70);
336 DECLARE_MSM_GPIO_PINS(71);
337 DECLARE_MSM_GPIO_PINS(72);
338 DECLARE_MSM_GPIO_PINS(73);
339 DECLARE_MSM_GPIO_PINS(74);
340 DECLARE_MSM_GPIO_PINS(75);
341 DECLARE_MSM_GPIO_PINS(76);
342 DECLARE_MSM_GPIO_PINS(77);
343 DECLARE_MSM_GPIO_PINS(78);
344 DECLARE_MSM_GPIO_PINS(79);
345 DECLARE_MSM_GPIO_PINS(80);
346 DECLARE_MSM_GPIO_PINS(81);
347 DECLARE_MSM_GPIO_PINS(82);
348 DECLARE_MSM_GPIO_PINS(83);
349 DECLARE_MSM_GPIO_PINS(84);
350 DECLARE_MSM_GPIO_PINS(85);
351 DECLARE_MSM_GPIO_PINS(86);
352 DECLARE_MSM_GPIO_PINS(87);
353 DECLARE_MSM_GPIO_PINS(88);
354 DECLARE_MSM_GPIO_PINS(89);
355 DECLARE_MSM_GPIO_PINS(90);
356 DECLARE_MSM_GPIO_PINS(91);
357 DECLARE_MSM_GPIO_PINS(92);
358 DECLARE_MSM_GPIO_PINS(93);
359 DECLARE_MSM_GPIO_PINS(94);
360 DECLARE_MSM_GPIO_PINS(95);
361 DECLARE_MSM_GPIO_PINS(96);
362 DECLARE_MSM_GPIO_PINS(97);
363 DECLARE_MSM_GPIO_PINS(98);
364 DECLARE_MSM_GPIO_PINS(99);
365 DECLARE_MSM_GPIO_PINS(100);
366 DECLARE_MSM_GPIO_PINS(101);
367 DECLARE_MSM_GPIO_PINS(102);
368 DECLARE_MSM_GPIO_PINS(103);
369 DECLARE_MSM_GPIO_PINS(104);
370 DECLARE_MSM_GPIO_PINS(105);
371 DECLARE_MSM_GPIO_PINS(106);
372 DECLARE_MSM_GPIO_PINS(107);
373 DECLARE_MSM_GPIO_PINS(108);
374 DECLARE_MSM_GPIO_PINS(109);
375 DECLARE_MSM_GPIO_PINS(110);
376 DECLARE_MSM_GPIO_PINS(111);
377 DECLARE_MSM_GPIO_PINS(112);
378 DECLARE_MSM_GPIO_PINS(113);
379 DECLARE_MSM_GPIO_PINS(114);
380 DECLARE_MSM_GPIO_PINS(115);
381 DECLARE_MSM_GPIO_PINS(116);
382 DECLARE_MSM_GPIO_PINS(117);
383 DECLARE_MSM_GPIO_PINS(118);
384 DECLARE_MSM_GPIO_PINS(119);
385 DECLARE_MSM_GPIO_PINS(120);
386 DECLARE_MSM_GPIO_PINS(121);
387 DECLARE_MSM_GPIO_PINS(122);
388 DECLARE_MSM_GPIO_PINS(123);
389 DECLARE_MSM_GPIO_PINS(124);
390 DECLARE_MSM_GPIO_PINS(125);
391 DECLARE_MSM_GPIO_PINS(126);
392 DECLARE_MSM_GPIO_PINS(127);
393 DECLARE_MSM_GPIO_PINS(128);
394 DECLARE_MSM_GPIO_PINS(129);
395 DECLARE_MSM_GPIO_PINS(130);
396 DECLARE_MSM_GPIO_PINS(131);
397 DECLARE_MSM_GPIO_PINS(132);
398 DECLARE_MSM_GPIO_PINS(133);
399 DECLARE_MSM_GPIO_PINS(134);
400 DECLARE_MSM_GPIO_PINS(135);
401 DECLARE_MSM_GPIO_PINS(136);
402 DECLARE_MSM_GPIO_PINS(137);
403 DECLARE_MSM_GPIO_PINS(138);
404 DECLARE_MSM_GPIO_PINS(139);
405 DECLARE_MSM_GPIO_PINS(140);
406 DECLARE_MSM_GPIO_PINS(141);
407 DECLARE_MSM_GPIO_PINS(142);
408 DECLARE_MSM_GPIO_PINS(143);
409 DECLARE_MSM_GPIO_PINS(144);
410 DECLARE_MSM_GPIO_PINS(145);
411 DECLARE_MSM_GPIO_PINS(146);
412 DECLARE_MSM_GPIO_PINS(147);
413 DECLARE_MSM_GPIO_PINS(148);
414 DECLARE_MSM_GPIO_PINS(149);
415 
416 static const unsigned int ufs_reset_pins[] = { 150 };
417 static const unsigned int sdc2_clk_pins[] = { 151 };
418 static const unsigned int sdc2_cmd_pins[] = { 152 };
419 static const unsigned int sdc2_data_pins[] = { 153 };
420 
421 enum sdm845_functions {
422 	msm_mux_gpio,
423 	msm_mux_adsp_ext,
424 	msm_mux_agera_pll,
425 	msm_mux_atest_char,
426 	msm_mux_atest_tsens,
427 	msm_mux_atest_tsens2,
428 	msm_mux_atest_usb1,
429 	msm_mux_atest_usb10,
430 	msm_mux_atest_usb11,
431 	msm_mux_atest_usb12,
432 	msm_mux_atest_usb13,
433 	msm_mux_atest_usb2,
434 	msm_mux_atest_usb20,
435 	msm_mux_atest_usb21,
436 	msm_mux_atest_usb22,
437 	msm_mux_atest_usb23,
438 	msm_mux_audio_ref,
439 	msm_mux_btfm_slimbus,
440 	msm_mux_cam_mclk,
441 	msm_mux_cci_async,
442 	msm_mux_cci_i2c,
443 	msm_mux_cci_timer0,
444 	msm_mux_cci_timer1,
445 	msm_mux_cci_timer2,
446 	msm_mux_cci_timer3,
447 	msm_mux_cci_timer4,
448 	msm_mux_cri_trng,
449 	msm_mux_cri_trng0,
450 	msm_mux_cri_trng1,
451 	msm_mux_dbg_out,
452 	msm_mux_ddr_bist,
453 	msm_mux_ddr_pxi0,
454 	msm_mux_ddr_pxi1,
455 	msm_mux_ddr_pxi2,
456 	msm_mux_ddr_pxi3,
457 	msm_mux_edp_hot,
458 	msm_mux_edp_lcd,
459 	msm_mux_gcc_gp1,
460 	msm_mux_gcc_gp2,
461 	msm_mux_gcc_gp3,
462 	msm_mux_jitter_bist,
463 	msm_mux_ldo_en,
464 	msm_mux_ldo_update,
465 	msm_mux_lpass_slimbus,
466 	msm_mux_m_voc,
467 	msm_mux_mdp_vsync,
468 	msm_mux_mdp_vsync0,
469 	msm_mux_mdp_vsync1,
470 	msm_mux_mdp_vsync2,
471 	msm_mux_mdp_vsync3,
472 	msm_mux_mss_lte,
473 	msm_mux_nav_pps,
474 	msm_mux_pa_indicator,
475 	msm_mux_pci_e0,
476 	msm_mux_pci_e1,
477 	msm_mux_phase_flag,
478 	msm_mux_pll_bist,
479 	msm_mux_pll_bypassnl,
480 	msm_mux_pll_reset,
481 	msm_mux_pri_mi2s,
482 	msm_mux_pri_mi2s_ws,
483 	msm_mux_prng_rosc,
484 	msm_mux_qdss_cti,
485 	msm_mux_qdss,
486 	msm_mux_qlink_enable,
487 	msm_mux_qlink_request,
488 	msm_mux_qspi_clk,
489 	msm_mux_qspi_cs,
490 	msm_mux_qspi_data,
491 	msm_mux_qua_mi2s,
492 	msm_mux_qup0,
493 	msm_mux_qup1,
494 	msm_mux_qup10,
495 	msm_mux_qup11,
496 	msm_mux_qup12,
497 	msm_mux_qup13,
498 	msm_mux_qup14,
499 	msm_mux_qup15,
500 	msm_mux_qup2,
501 	msm_mux_qup3,
502 	msm_mux_qup4,
503 	msm_mux_qup5,
504 	msm_mux_qup6,
505 	msm_mux_qup7,
506 	msm_mux_qup8,
507 	msm_mux_qup9,
508 	msm_mux_qup_l4,
509 	msm_mux_qup_l5,
510 	msm_mux_qup_l6,
511 	msm_mux_sd_write,
512 	msm_mux_sdc4_clk,
513 	msm_mux_sdc4_cmd,
514 	msm_mux_sdc4_data,
515 	msm_mux_sec_mi2s,
516 	msm_mux_sp_cmu,
517 	msm_mux_spkr_i2s,
518 	msm_mux_ter_mi2s,
519 	msm_mux_tgu_ch0,
520 	msm_mux_tgu_ch1,
521 	msm_mux_tgu_ch2,
522 	msm_mux_tgu_ch3,
523 	msm_mux_tsense_pwm1,
524 	msm_mux_tsense_pwm2,
525 	msm_mux_tsif1_clk,
526 	msm_mux_tsif1_data,
527 	msm_mux_tsif1_en,
528 	msm_mux_tsif1_error,
529 	msm_mux_tsif1_sync,
530 	msm_mux_tsif2_clk,
531 	msm_mux_tsif2_data,
532 	msm_mux_tsif2_en,
533 	msm_mux_tsif2_error,
534 	msm_mux_tsif2_sync,
535 	msm_mux_uim1_clk,
536 	msm_mux_uim1_data,
537 	msm_mux_uim1_present,
538 	msm_mux_uim1_reset,
539 	msm_mux_uim2_clk,
540 	msm_mux_uim2_data,
541 	msm_mux_uim2_present,
542 	msm_mux_uim2_reset,
543 	msm_mux_uim_batt,
544 	msm_mux_usb_phy,
545 	msm_mux_vfr_1,
546 	msm_mux_vsense_trigger,
547 	msm_mux_wlan1_adc0,
548 	msm_mux_wlan1_adc1,
549 	msm_mux_wlan2_adc0,
550 	msm_mux_wlan2_adc1,
551 	msm_mux__,
552 };
553 
554 static const char * const ddr_pxi3_groups[] = {
555 	"gpio12", "gpio13",
556 };
557 static const char * const cam_mclk_groups[] = {
558 	"gpio13", "gpio14", "gpio15", "gpio16",
559 };
560 static const char * const pll_bypassnl_groups[] = {
561 	"gpio13",
562 };
563 static const char * const qdss_groups[] = {
564 	"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
565 	"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
566 	"gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
567 	"gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
568 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
569 	"gpio123", "gpio124",
570 };
571 static const char * const pll_reset_groups[] = {
572 	"gpio14",
573 };
574 static const char * const cci_i2c_groups[] = {
575 	"gpio17", "gpio18", "gpio19", "gpio20",
576 };
577 static const char * const qup1_groups[] = {
578 	"gpio17", "gpio18", "gpio19", "gpio20",
579 };
580 static const char * const cci_timer0_groups[] = {
581 	"gpio21",
582 };
583 static const char * const gcc_gp2_groups[] = {
584 	"gpio21", "gpio58",
585 };
586 static const char * const cci_timer1_groups[] = {
587 	"gpio22",
588 };
589 static const char * const gcc_gp3_groups[] = {
590 	"gpio22", "gpio59",
591 };
592 static const char * const cci_timer2_groups[] = {
593 	"gpio23",
594 };
595 static const char * const cci_timer3_groups[] = {
596 	"gpio24",
597 };
598 static const char * const cci_async_groups[] = {
599 	"gpio24", "gpio25", "gpio26",
600 };
601 static const char * const cci_timer4_groups[] = {
602 	"gpio25",
603 };
604 static const char * const qup2_groups[] = {
605 	"gpio27", "gpio28", "gpio29", "gpio30",
606 };
607 static const char * const phase_flag_groups[] = {
608 	"gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
609 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
610 	"gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
611 	"gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
612 	"gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
613 };
614 static const char * const qup11_groups[] = {
615 	"gpio31", "gpio32", "gpio33", "gpio34",
616 };
617 static const char * const qup14_groups[] = {
618 	"gpio31", "gpio32", "gpio33", "gpio34",
619 };
620 static const char * const pci_e0_groups[] = {
621 	"gpio35", "gpio36",
622 };
623 static const char * const jitter_bist_groups[] = {
624 	"gpio35",
625 };
626 static const char * const pll_bist_groups[] = {
627 	"gpio36",
628 };
629 static const char * const atest_tsens_groups[] = {
630 	"gpio36",
631 };
632 static const char * const agera_pll_groups[] = {
633 	"gpio37",
634 };
635 static const char * const usb_phy_groups[] = {
636 	"gpio38",
637 };
638 static const char * const lpass_slimbus_groups[] = {
639 	"gpio39", "gpio70", "gpio71", "gpio72",
640 };
641 static const char * const sd_write_groups[] = {
642 	"gpio40",
643 };
644 static const char * const tsif1_error_groups[] = {
645 	"gpio40",
646 };
647 static const char * const qup3_groups[] = {
648 	"gpio41", "gpio42", "gpio43", "gpio44",
649 };
650 static const char * const qup6_groups[] = {
651 	"gpio45", "gpio46", "gpio47", "gpio48",
652 };
653 static const char * const qup12_groups[] = {
654 	"gpio49", "gpio50", "gpio51", "gpio52",
655 };
656 static const char * const qup10_groups[] = {
657 	"gpio53", "gpio54", "gpio55", "gpio56",
658 };
659 static const char * const qua_mi2s_groups[] = {
660 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
661 };
662 static const char * const gcc_gp1_groups[] = {
663 	"gpio57", "gpio78",
664 };
665 static const char * const cri_trng0_groups[] = {
666 	"gpio60",
667 };
668 static const char * const cri_trng1_groups[] = {
669 	"gpio61",
670 };
671 static const char * const cri_trng_groups[] = {
672 	"gpio62",
673 };
674 static const char * const pri_mi2s_groups[] = {
675 	"gpio64", "gpio65", "gpio67", "gpio68",
676 };
677 static const char * const sp_cmu_groups[] = {
678 	"gpio64",
679 };
680 static const char * const qup8_groups[] = {
681 	"gpio65", "gpio66", "gpio67", "gpio68",
682 };
683 static const char * const pri_mi2s_ws_groups[] = {
684 	"gpio66",
685 };
686 static const char * const spkr_i2s_groups[] = {
687 	"gpio69", "gpio70", "gpio71", "gpio72",
688 };
689 static const char * const audio_ref_groups[] = {
690 	"gpio69",
691 };
692 static const char * const tsense_pwm1_groups[] = {
693 	"gpio71",
694 };
695 static const char * const tsense_pwm2_groups[] = {
696 	"gpio71",
697 };
698 static const char * const btfm_slimbus_groups[] = {
699 	"gpio73", "gpio74",
700 };
701 static const char * const atest_usb2_groups[] = {
702 	"gpio73",
703 };
704 static const char * const ter_mi2s_groups[] = {
705 	"gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
706 };
707 static const char * const atest_usb23_groups[] = {
708 	"gpio74",
709 };
710 static const char * const atest_usb22_groups[] = {
711 	"gpio75",
712 };
713 static const char * const atest_usb21_groups[] = {
714 	"gpio76",
715 };
716 static const char * const atest_usb20_groups[] = {
717 	"gpio77",
718 };
719 static const char * const sec_mi2s_groups[] = {
720 	"gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
721 };
722 static const char * const qup15_groups[] = {
723 	"gpio81", "gpio82", "gpio83", "gpio84",
724 };
725 static const char * const qup5_groups[] = {
726 	"gpio85", "gpio86", "gpio87", "gpio88",
727 };
728 static const char * const tsif1_clk_groups[] = {
729 	"gpio89",
730 };
731 static const char * const qup4_groups[] = {
732 	"gpio89", "gpio90", "gpio91", "gpio92",
733 };
734 static const char * const qspi_cs_groups[] = {
735 	"gpio89", "gpio90",
736 };
737 static const char * const tgu_ch3_groups[] = {
738 	"gpio89",
739 };
740 static const char * const tsif1_en_groups[] = {
741 	"gpio90",
742 };
743 static const char * const mdp_vsync0_groups[] = {
744 	"gpio90",
745 };
746 static const char * const mdp_vsync1_groups[] = {
747 	"gpio90",
748 };
749 static const char * const mdp_vsync2_groups[] = {
750 	"gpio90",
751 };
752 static const char * const mdp_vsync3_groups[] = {
753 	"gpio90",
754 };
755 static const char * const tgu_ch0_groups[] = {
756 	"gpio90",
757 };
758 static const char * const tsif1_data_groups[] = {
759 	"gpio91",
760 };
761 static const char * const sdc4_cmd_groups[] = {
762 	"gpio91",
763 };
764 static const char * const qspi_data_groups[] = {
765 	"gpio91", "gpio92", "gpio93", "gpio94",
766 };
767 static const char * const tgu_ch1_groups[] = {
768 	"gpio91",
769 };
770 static const char * const tsif2_error_groups[] = {
771 	"gpio92",
772 };
773 static const char * const sdc4_data_groups[] = {
774 	"gpio92",
775 	"gpio94",
776 	"gpio95",
777 	"gpio96",
778 };
779 static const char * const vfr_1_groups[] = {
780 	"gpio92",
781 };
782 static const char * const tgu_ch2_groups[] = {
783 	"gpio92",
784 };
785 static const char * const tsif2_clk_groups[] = {
786 	"gpio93",
787 };
788 static const char * const sdc4_clk_groups[] = {
789 	"gpio93",
790 };
791 static const char * const qup7_groups[] = {
792 	"gpio93", "gpio94", "gpio95", "gpio96",
793 };
794 static const char * const tsif2_en_groups[] = {
795 	"gpio94",
796 };
797 static const char * const tsif2_data_groups[] = {
798 	"gpio95",
799 };
800 static const char * const qspi_clk_groups[] = {
801 	"gpio95",
802 };
803 static const char * const tsif2_sync_groups[] = {
804 	"gpio96",
805 };
806 static const char * const ldo_en_groups[] = {
807 	"gpio97",
808 };
809 static const char * const ldo_update_groups[] = {
810 	"gpio98",
811 };
812 static const char * const pci_e1_groups[] = {
813 	"gpio102", "gpio103",
814 };
815 static const char * const prng_rosc_groups[] = {
816 	"gpio102",
817 };
818 static const char * const uim2_data_groups[] = {
819 	"gpio105",
820 };
821 static const char * const qup13_groups[] = {
822 	"gpio105", "gpio106", "gpio107", "gpio108",
823 };
824 static const char * const uim2_clk_groups[] = {
825 	"gpio106",
826 };
827 static const char * const uim2_reset_groups[] = {
828 	"gpio107",
829 };
830 static const char * const uim2_present_groups[] = {
831 	"gpio108",
832 };
833 static const char * const uim1_data_groups[] = {
834 	"gpio109",
835 };
836 static const char * const uim1_clk_groups[] = {
837 	"gpio110",
838 };
839 static const char * const uim1_reset_groups[] = {
840 	"gpio111",
841 };
842 static const char * const uim1_present_groups[] = {
843 	"gpio112",
844 };
845 static const char * const uim_batt_groups[] = {
846 	"gpio113",
847 };
848 static const char * const edp_hot_groups[] = {
849 	"gpio113",
850 };
851 static const char * const nav_pps_groups[] = {
852 	"gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
853 	"gpio129", "gpio129", "gpio143", "gpio143",
854 };
855 static const char * const atest_char_groups[] = {
856 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
857 };
858 static const char * const adsp_ext_groups[] = {
859 	"gpio118",
860 };
861 static const char * const qlink_request_groups[] = {
862 	"gpio130",
863 };
864 static const char * const qlink_enable_groups[] = {
865 	"gpio131",
866 };
867 static const char * const pa_indicator_groups[] = {
868 	"gpio135",
869 };
870 static const char * const mss_lte_groups[] = {
871 	"gpio144", "gpio145",
872 };
873 static const char * const qup0_groups[] = {
874 	"gpio0", "gpio1", "gpio2", "gpio3",
875 };
876 static const char * const gpio_groups[] = {
877 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
878 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
879 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
880 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
881 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
882 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
883 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
884 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
885 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
886 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
887 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
888 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
889 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
890 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
891 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
892 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
893 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
894 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
895 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
896 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
897 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
898 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
899 	"gpio147", "gpio148", "gpio149",
900 };
901 static const char * const qup9_groups[] = {
902 	"gpio4", "gpio5", "gpio6", "gpio7",
903 };
904 static const char * const qdss_cti_groups[] = {
905 	"gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
906 	"gpio91",
907 };
908 static const char * const ddr_pxi0_groups[] = {
909 	"gpio6", "gpio7",
910 };
911 static const char * const ddr_bist_groups[] = {
912 	"gpio7", "gpio8", "gpio9", "gpio10",
913 };
914 static const char * const atest_tsens2_groups[] = {
915 	"gpio7",
916 };
917 static const char * const vsense_trigger_groups[] = {
918 	"gpio7",
919 };
920 static const char * const atest_usb1_groups[] = {
921 	"gpio7",
922 };
923 static const char * const qup_l4_groups[] = {
924 	"gpio8", "gpio35", "gpio105", "gpio123",
925 };
926 static const char * const wlan1_adc1_groups[] = {
927 	"gpio8",
928 };
929 static const char * const atest_usb13_groups[] = {
930 	"gpio8",
931 };
932 static const char * const ddr_pxi1_groups[] = {
933 	"gpio8", "gpio9",
934 };
935 static const char * const qup_l5_groups[] = {
936 	"gpio9", "gpio36", "gpio106", "gpio124",
937 };
938 static const char * const wlan1_adc0_groups[] = {
939 	"gpio9",
940 };
941 static const char * const atest_usb12_groups[] = {
942 	"gpio9",
943 };
944 static const char * const mdp_vsync_groups[] = {
945 	"gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
946 };
947 static const char * const qup_l6_groups[] = {
948 	"gpio10", "gpio37", "gpio107", "gpio125",
949 };
950 static const char * const wlan2_adc1_groups[] = {
951 	"gpio10",
952 };
953 static const char * const atest_usb11_groups[] = {
954 	"gpio10",
955 };
956 static const char * const ddr_pxi2_groups[] = {
957 	"gpio10", "gpio11",
958 };
959 static const char * const edp_lcd_groups[] = {
960 	"gpio11",
961 };
962 static const char * const dbg_out_groups[] = {
963 	"gpio11",
964 };
965 static const char * const wlan2_adc0_groups[] = {
966 	"gpio11",
967 };
968 static const char * const atest_usb10_groups[] = {
969 	"gpio11",
970 };
971 static const char * const m_voc_groups[] = {
972 	"gpio12",
973 };
974 static const char * const tsif1_sync_groups[] = {
975 	"gpio12",
976 };
977 
978 static const struct pinfunction sdm845_functions[] = {
979 	MSM_PIN_FUNCTION(gpio),
980 	MSM_PIN_FUNCTION(adsp_ext),
981 	MSM_PIN_FUNCTION(agera_pll),
982 	MSM_PIN_FUNCTION(atest_char),
983 	MSM_PIN_FUNCTION(atest_tsens),
984 	MSM_PIN_FUNCTION(atest_tsens2),
985 	MSM_PIN_FUNCTION(atest_usb1),
986 	MSM_PIN_FUNCTION(atest_usb10),
987 	MSM_PIN_FUNCTION(atest_usb11),
988 	MSM_PIN_FUNCTION(atest_usb12),
989 	MSM_PIN_FUNCTION(atest_usb13),
990 	MSM_PIN_FUNCTION(atest_usb2),
991 	MSM_PIN_FUNCTION(atest_usb20),
992 	MSM_PIN_FUNCTION(atest_usb21),
993 	MSM_PIN_FUNCTION(atest_usb22),
994 	MSM_PIN_FUNCTION(atest_usb23),
995 	MSM_PIN_FUNCTION(audio_ref),
996 	MSM_PIN_FUNCTION(btfm_slimbus),
997 	MSM_PIN_FUNCTION(cam_mclk),
998 	MSM_PIN_FUNCTION(cci_async),
999 	MSM_PIN_FUNCTION(cci_i2c),
1000 	MSM_PIN_FUNCTION(cci_timer0),
1001 	MSM_PIN_FUNCTION(cci_timer1),
1002 	MSM_PIN_FUNCTION(cci_timer2),
1003 	MSM_PIN_FUNCTION(cci_timer3),
1004 	MSM_PIN_FUNCTION(cci_timer4),
1005 	MSM_PIN_FUNCTION(cri_trng),
1006 	MSM_PIN_FUNCTION(cri_trng0),
1007 	MSM_PIN_FUNCTION(cri_trng1),
1008 	MSM_PIN_FUNCTION(dbg_out),
1009 	MSM_PIN_FUNCTION(ddr_bist),
1010 	MSM_PIN_FUNCTION(ddr_pxi0),
1011 	MSM_PIN_FUNCTION(ddr_pxi1),
1012 	MSM_PIN_FUNCTION(ddr_pxi2),
1013 	MSM_PIN_FUNCTION(ddr_pxi3),
1014 	MSM_PIN_FUNCTION(edp_hot),
1015 	MSM_PIN_FUNCTION(edp_lcd),
1016 	MSM_PIN_FUNCTION(gcc_gp1),
1017 	MSM_PIN_FUNCTION(gcc_gp2),
1018 	MSM_PIN_FUNCTION(gcc_gp3),
1019 	MSM_PIN_FUNCTION(jitter_bist),
1020 	MSM_PIN_FUNCTION(ldo_en),
1021 	MSM_PIN_FUNCTION(ldo_update),
1022 	MSM_PIN_FUNCTION(lpass_slimbus),
1023 	MSM_PIN_FUNCTION(m_voc),
1024 	MSM_PIN_FUNCTION(mdp_vsync),
1025 	MSM_PIN_FUNCTION(mdp_vsync0),
1026 	MSM_PIN_FUNCTION(mdp_vsync1),
1027 	MSM_PIN_FUNCTION(mdp_vsync2),
1028 	MSM_PIN_FUNCTION(mdp_vsync3),
1029 	MSM_PIN_FUNCTION(mss_lte),
1030 	MSM_PIN_FUNCTION(nav_pps),
1031 	MSM_PIN_FUNCTION(pa_indicator),
1032 	MSM_PIN_FUNCTION(pci_e0),
1033 	MSM_PIN_FUNCTION(pci_e1),
1034 	MSM_PIN_FUNCTION(phase_flag),
1035 	MSM_PIN_FUNCTION(pll_bist),
1036 	MSM_PIN_FUNCTION(pll_bypassnl),
1037 	MSM_PIN_FUNCTION(pll_reset),
1038 	MSM_PIN_FUNCTION(pri_mi2s),
1039 	MSM_PIN_FUNCTION(pri_mi2s_ws),
1040 	MSM_PIN_FUNCTION(prng_rosc),
1041 	MSM_PIN_FUNCTION(qdss_cti),
1042 	MSM_PIN_FUNCTION(qdss),
1043 	MSM_PIN_FUNCTION(qlink_enable),
1044 	MSM_PIN_FUNCTION(qlink_request),
1045 	MSM_PIN_FUNCTION(qspi_clk),
1046 	MSM_PIN_FUNCTION(qspi_cs),
1047 	MSM_PIN_FUNCTION(qspi_data),
1048 	MSM_PIN_FUNCTION(qua_mi2s),
1049 	MSM_PIN_FUNCTION(qup0),
1050 	MSM_PIN_FUNCTION(qup1),
1051 	MSM_PIN_FUNCTION(qup10),
1052 	MSM_PIN_FUNCTION(qup11),
1053 	MSM_PIN_FUNCTION(qup12),
1054 	MSM_PIN_FUNCTION(qup13),
1055 	MSM_PIN_FUNCTION(qup14),
1056 	MSM_PIN_FUNCTION(qup15),
1057 	MSM_PIN_FUNCTION(qup2),
1058 	MSM_PIN_FUNCTION(qup3),
1059 	MSM_PIN_FUNCTION(qup4),
1060 	MSM_PIN_FUNCTION(qup5),
1061 	MSM_PIN_FUNCTION(qup6),
1062 	MSM_PIN_FUNCTION(qup7),
1063 	MSM_PIN_FUNCTION(qup8),
1064 	MSM_PIN_FUNCTION(qup9),
1065 	MSM_PIN_FUNCTION(qup_l4),
1066 	MSM_PIN_FUNCTION(qup_l5),
1067 	MSM_PIN_FUNCTION(qup_l6),
1068 	MSM_PIN_FUNCTION(sd_write),
1069 	MSM_PIN_FUNCTION(sdc4_clk),
1070 	MSM_PIN_FUNCTION(sdc4_cmd),
1071 	MSM_PIN_FUNCTION(sdc4_data),
1072 	MSM_PIN_FUNCTION(sec_mi2s),
1073 	MSM_PIN_FUNCTION(sp_cmu),
1074 	MSM_PIN_FUNCTION(spkr_i2s),
1075 	MSM_PIN_FUNCTION(ter_mi2s),
1076 	MSM_PIN_FUNCTION(tgu_ch0),
1077 	MSM_PIN_FUNCTION(tgu_ch1),
1078 	MSM_PIN_FUNCTION(tgu_ch2),
1079 	MSM_PIN_FUNCTION(tgu_ch3),
1080 	MSM_PIN_FUNCTION(tsense_pwm1),
1081 	MSM_PIN_FUNCTION(tsense_pwm2),
1082 	MSM_PIN_FUNCTION(tsif1_clk),
1083 	MSM_PIN_FUNCTION(tsif1_data),
1084 	MSM_PIN_FUNCTION(tsif1_en),
1085 	MSM_PIN_FUNCTION(tsif1_error),
1086 	MSM_PIN_FUNCTION(tsif1_sync),
1087 	MSM_PIN_FUNCTION(tsif2_clk),
1088 	MSM_PIN_FUNCTION(tsif2_data),
1089 	MSM_PIN_FUNCTION(tsif2_en),
1090 	MSM_PIN_FUNCTION(tsif2_error),
1091 	MSM_PIN_FUNCTION(tsif2_sync),
1092 	MSM_PIN_FUNCTION(uim1_clk),
1093 	MSM_PIN_FUNCTION(uim1_data),
1094 	MSM_PIN_FUNCTION(uim1_present),
1095 	MSM_PIN_FUNCTION(uim1_reset),
1096 	MSM_PIN_FUNCTION(uim2_clk),
1097 	MSM_PIN_FUNCTION(uim2_data),
1098 	MSM_PIN_FUNCTION(uim2_present),
1099 	MSM_PIN_FUNCTION(uim2_reset),
1100 	MSM_PIN_FUNCTION(uim_batt),
1101 	MSM_PIN_FUNCTION(usb_phy),
1102 	MSM_PIN_FUNCTION(vfr_1),
1103 	MSM_PIN_FUNCTION(vsense_trigger),
1104 	MSM_PIN_FUNCTION(wlan1_adc0),
1105 	MSM_PIN_FUNCTION(wlan1_adc1),
1106 	MSM_PIN_FUNCTION(wlan2_adc0),
1107 	MSM_PIN_FUNCTION(wlan2_adc1),
1108 };
1109 
1110 /* Every pin is maintained as a single group, and missing or non-existing pin
1111  * would be maintained as dummy group to synchronize pin group index with
1112  * pin descriptor registered with pinctrl core.
1113  * Clients would not be able to request these dummy pin groups.
1114  */
1115 static const struct msm_pingroup sdm845_groups[] = {
1116 	PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
1117 	PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
1118 	PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
1119 	PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
1120 	PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1121 	PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1122 	PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
1123 	PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1124 	PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1125 	PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
1126 	PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
1127 	PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
1128 	PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
1129 	PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
1130 	PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
1131 	PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1132 	PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1133 	PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
1134 	PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1135 	PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1136 	PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1137 	PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
1138 	PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
1139 	PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
1140 	PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
1141 	PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
1142 	PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
1143 	PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1144 	PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1145 	PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
1146 	PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
1147 	PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1148 	PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1149 	PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1150 	PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1151 	PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
1152 	PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
1153 	PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
1154 	PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
1155 	PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
1156 	PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
1157 	PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1158 	PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1159 	PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1160 	PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1161 	PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
1162 	PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
1163 	PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
1164 	PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
1165 	PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1166 	PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1167 	PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
1168 	PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
1169 	PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1170 	PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
1171 	PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1172 	PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1173 	PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
1174 	PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
1175 	PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
1176 	PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
1177 	PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
1178 	PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
1179 	PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
1180 	PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
1181 	PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1182 	PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
1183 	PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1184 	PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1185 	PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
1186 	PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1187 	PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1188 	PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1189 	PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
1190 	PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
1191 	PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
1192 	PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
1193 	PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
1194 	PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
1195 	PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
1196 	PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
1197 	PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1198 	PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1199 	PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1200 	PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
1201 	PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
1202 	PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
1203 	PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
1204 	PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
1205 	PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
1206 	PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
1207 			    mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1208 	PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
1209 	PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
1210 	PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
1211 	PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
1212 	PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
1213 	PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
1214 	PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
1215 	PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1216 	PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1217 	PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1218 	PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
1219 	PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
1220 	PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
1221 	PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
1222 	PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
1223 	PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
1224 	PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
1225 	PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
1226 	PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
1227 	PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
1228 	PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
1229 	PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
1230 	PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
1231 	PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1232 	PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1233 	PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
1234 	PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1235 	PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
1236 	PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1237 	PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1238 	PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1239 	PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
1240 	PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
1241 	PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
1242 	PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
1243 	PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
1244 	PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
1245 	PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1246 	PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1247 	PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
1248 	PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
1249 	PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
1250 	PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
1251 	PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
1252 	PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
1253 	PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
1254 	PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1255 	PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1256 	PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1257 	PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1258 	PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1259 	PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1260 	PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
1261 	PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1262 	PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1263 	PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
1264 	PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
1265 	PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
1266 	PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
1267 	UFS_RESET(ufs_reset, 0x99f000),
1268 	SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
1269 	SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
1270 	SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
1271 };
1272 
1273 static const int sdm845_acpi_reserved_gpios[] = {
1274 	0, 1, 2, 3, 81, 82, 83, 84, -1
1275 };
1276 
1277 static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = {
1278 	{ 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
1279 	{ 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
1280 	{ 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
1281 	{ 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
1282 	{ 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
1283 	{ 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 },
1284 	{ 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 },
1285 	{ 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 },
1286 	{ 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 },
1287 	{ 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 },
1288 	{ 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 },
1289 	{ 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
1290 	{ 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
1291 	{ 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
1292 	{ 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
1293 };
1294 
1295 static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
1296 	.pins = sdm845_pins,
1297 	.npins = ARRAY_SIZE(sdm845_pins),
1298 	.functions = sdm845_functions,
1299 	.nfunctions = ARRAY_SIZE(sdm845_functions),
1300 	.groups = sdm845_groups,
1301 	.ngroups = ARRAY_SIZE(sdm845_groups),
1302 	.ngpios = 151,
1303 	.wakeirq_map = sdm845_pdc_map,
1304 	.nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map),
1305 	.wakeirq_dual_edge_errata = true,
1306 };
1307 
1308 static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
1309 	.pins = sdm845_pins,
1310 	.npins = ARRAY_SIZE(sdm845_pins),
1311 	.groups = sdm845_groups,
1312 	.ngroups = ARRAY_SIZE(sdm845_groups),
1313 	.reserved_gpios = sdm845_acpi_reserved_gpios,
1314 	.ngpios = 150,
1315 };
1316 
sdm845_pinctrl_probe(struct platform_device * pdev)1317 static int sdm845_pinctrl_probe(struct platform_device *pdev)
1318 {
1319 	int ret;
1320 
1321 	if (pdev->dev.of_node) {
1322 		ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1323 	} else if (has_acpi_companion(&pdev->dev)) {
1324 		ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
1325 	} else {
1326 		dev_err(&pdev->dev, "DT and ACPI disabled\n");
1327 		return -EINVAL;
1328 	}
1329 
1330 	return ret;
1331 }
1332 
1333 #ifdef CONFIG_ACPI
1334 static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
1335 	{ "QCOM0217"},
1336 	{ },
1337 };
1338 MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
1339 #endif
1340 
1341 static const struct of_device_id sdm845_pinctrl_of_match[] = {
1342 	{ .compatible = "qcom,sdm845-pinctrl", },
1343 	{ },
1344 };
1345 
1346 static struct platform_driver sdm845_pinctrl_driver = {
1347 	.driver = {
1348 		.name = "sdm845-pinctrl",
1349 		.pm = &msm_pinctrl_dev_pm_ops,
1350 		.of_match_table = sdm845_pinctrl_of_match,
1351 		.acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
1352 	},
1353 	.probe = sdm845_pinctrl_probe,
1354 	.remove_new = msm_pinctrl_remove,
1355 };
1356 
sdm845_pinctrl_init(void)1357 static int __init sdm845_pinctrl_init(void)
1358 {
1359 	return platform_driver_register(&sdm845_pinctrl_driver);
1360 }
1361 arch_initcall(sdm845_pinctrl_init);
1362 
sdm845_pinctrl_exit(void)1363 static void __exit sdm845_pinctrl_exit(void)
1364 {
1365 	platform_driver_unregister(&sdm845_pinctrl_driver);
1366 }
1367 module_exit(sdm845_pinctrl_exit);
1368 
1369 MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
1370 MODULE_LICENSE("GPL v2");
1371 MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
1372