1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HW_H
8 #define ATH12K_HW_H
9
10 #include <linux/mhi.h>
11 #include <linux/uuid.h>
12
13 #include "wmi.h"
14 #include "hal.h"
15
16 /* Target configuration defines */
17
18 /* Num VDEVS per radio */
19 #define TARGET_NUM_VDEVS (16 + 1)
20
21 #define TARGET_NUM_PEERS_PDEV_SINGLE (TARGET_NUM_STATIONS_SINGLE + \
22 TARGET_NUM_VDEVS)
23 #define TARGET_NUM_PEERS_PDEV_DBS (TARGET_NUM_STATIONS_DBS + \
24 TARGET_NUM_VDEVS)
25 #define TARGET_NUM_PEERS_PDEV_DBS_SBS (TARGET_NUM_STATIONS_DBS_SBS + \
26 TARGET_NUM_VDEVS)
27
28 /* Num of peers for Single Radio mode */
29 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV_SINGLE)
30
31 /* Num of peers for DBS */
32 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV_DBS)
33
34 /* Num of peers for DBS_SBS */
35 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV_DBS_SBS)
36
37 /* Max num of stations for Single Radio mode */
38 #define TARGET_NUM_STATIONS_SINGLE 512
39
40 /* Max num of stations for DBS */
41 #define TARGET_NUM_STATIONS_DBS 128
42
43 /* Max num of stations for DBS_SBS */
44 #define TARGET_NUM_STATIONS_DBS_SBS 128
45
46 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x
47 #define TARGET_NUM_PEER_KEYS 2
48 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \
49 4 * TARGET_NUM_VDEVS + 8)
50
51 #define TARGET_AST_SKID_LIMIT 16
52 #define TARGET_NUM_OFFLD_PEERS 4
53 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
54
55 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
56 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
57 #define TARGET_RX_TIMEOUT_LO_PRI 100
58 #define TARGET_RX_TIMEOUT_HI_PRI 40
59
60 #define TARGET_DECAP_MODE_RAW 0
61 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
62 #define TARGET_DECAP_MODE_ETH 2
63
64 #define TARGET_SCAN_MAX_PENDING_REQS 4
65 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
66 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
67 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
68 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
69 #define TARGET_NUM_MCAST_GROUPS 12
70 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
71 #define TARGET_MCAST2UCAST_MODE 2
72 #define TARGET_TX_DBG_LOG_SIZE 1024
73 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
74 #define TARGET_VOW_CONFIG 0
75 #define TARGET_NUM_MSDU_DESC (2500)
76 #define TARGET_MAX_FRAG_ENTRIES 6
77 #define TARGET_MAX_BCN_OFFLD 16
78 #define TARGET_NUM_WDS_ENTRIES 32
79 #define TARGET_DMA_BURST_SIZE 1
80 #define TARGET_RX_BATCHMODE 1
81 #define TARGET_EMA_MAX_PROFILE_PERIOD 8
82
83 #define ATH12K_HW_DEFAULT_QUEUE 0
84 #define ATH12K_HW_MAX_QUEUES 4
85 #define ATH12K_QUEUE_LEN 4096
86
87 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
88
89 #define ATH12K_FW_DIR "ath12k"
90
91 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD"
92 #define ATH12K_BOARD_API2_FILE "board-2.bin"
93 #define ATH12K_DEFAULT_BOARD_FILE "board.bin"
94 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin"
95 #define ATH12K_AMSS_FILE "amss.bin"
96 #define ATH12K_M3_FILE "m3.bin"
97 #define ATH12K_REGDB_FILE_NAME "regdb.bin"
98
99 #define ATH12K_PCIE_MAX_PAYLOAD_SIZE 128
100
101 enum ath12k_hw_rate_cck {
102 ATH12K_HW_RATE_CCK_LP_11M = 0,
103 ATH12K_HW_RATE_CCK_LP_5_5M,
104 ATH12K_HW_RATE_CCK_LP_2M,
105 ATH12K_HW_RATE_CCK_LP_1M,
106 ATH12K_HW_RATE_CCK_SP_11M,
107 ATH12K_HW_RATE_CCK_SP_5_5M,
108 ATH12K_HW_RATE_CCK_SP_2M,
109 };
110
111 enum ath12k_hw_rate_ofdm {
112 ATH12K_HW_RATE_OFDM_48M = 0,
113 ATH12K_HW_RATE_OFDM_24M,
114 ATH12K_HW_RATE_OFDM_12M,
115 ATH12K_HW_RATE_OFDM_6M,
116 ATH12K_HW_RATE_OFDM_54M,
117 ATH12K_HW_RATE_OFDM_36M,
118 ATH12K_HW_RATE_OFDM_18M,
119 ATH12K_HW_RATE_OFDM_9M,
120 };
121
122 enum ath12k_bus {
123 ATH12K_BUS_PCI,
124 };
125
126 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11
127
128 struct hal_rx_desc;
129 struct hal_tcl_data_cmd;
130 struct htt_rx_ring_tlv_filter;
131 enum hal_encrypt_type;
132
133 struct ath12k_hw_ring_mask {
134 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
135 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
136 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
137 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX];
138 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX];
139 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
140 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX];
141 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
142 };
143
144 struct ath12k_hw_hal_params {
145 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
146 u32 wbm2sw_cc_enable;
147 };
148
149 struct ath12k_hw_params {
150 const char *name;
151 u16 hw_rev;
152
153 struct {
154 const char *dir;
155 size_t board_size;
156 size_t cal_offset;
157 } fw;
158
159 u8 max_radios;
160 bool single_pdev_only:1;
161 u32 qmi_service_ins_id;
162 bool internal_sleep_clock:1;
163
164 const struct ath12k_hw_ops *hw_ops;
165 const struct ath12k_hw_ring_mask *ring_mask;
166 const struct ath12k_hw_regs *regs;
167
168 const struct ce_attr *host_ce_config;
169 u32 ce_count;
170 const struct ce_pipe_config *target_ce_config;
171 u32 target_ce_count;
172 const struct service_to_pipe *svc_to_ce_map;
173 u32 svc_to_ce_map_len;
174
175 const struct ath12k_hw_hal_params *hal_params;
176
177 bool rxdma1_enable:1;
178 int num_rxdma_per_pdev;
179 int num_rxdma_dst_ring;
180 bool rx_mac_buf_ring:1;
181 bool vdev_start_delay:1;
182
183 u16 interface_modes;
184 bool supports_monitor:1;
185
186 bool idle_ps:1;
187 bool download_calib:1;
188 bool supports_suspend:1;
189 bool tcl_ring_retry:1;
190 bool reoq_lut_support:1;
191 bool supports_shadow_regs:1;
192 bool supports_aspm:1;
193
194 u32 num_tcl_banks;
195 u32 max_tx_ring;
196
197 const struct mhi_controller_config *mhi_config;
198
199 void (*wmi_init)(struct ath12k_base *ab,
200 struct ath12k_wmi_resource_config_arg *config);
201
202 const struct hal_ops *hal_ops;
203
204 u64 qmi_cnss_feature_bitmap;
205
206 u32 rfkill_pin;
207 u32 rfkill_cfg;
208 u32 rfkill_on_level;
209
210 u32 rddm_size;
211
212 u8 def_num_link;
213 u16 max_mlo_peer;
214
215 u32 otp_board_id_register;
216
217 bool supports_sta_ps;
218
219 const guid_t *acpi_guid;
220 bool supports_dynamic_smps_6ghz;
221
222 u32 iova_mask;
223 };
224
225 struct ath12k_hw_ops {
226 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
227 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id);
228 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id);
229 int (*rxdma_ring_sel_config)(struct ath12k_base *ab);
230 u8 (*get_ring_selector)(struct sk_buff *skb);
231 bool (*dp_srng_is_tx_comp_ring)(int ring_num);
232 };
233
234 static inline
ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params * hw,int pdev_idx)235 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw,
236 int pdev_idx)
237 {
238 if (hw->hw_ops->get_hw_mac_from_pdev_id)
239 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
240
241 return 0;
242 }
243
ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params * hw,int mac_id)244 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw,
245 int mac_id)
246 {
247 if (hw->hw_ops->mac_id_to_pdev_id)
248 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
249
250 return 0;
251 }
252
ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params * hw,int mac_id)253 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw,
254 int mac_id)
255 {
256 if (hw->hw_ops->mac_id_to_srng_id)
257 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
258
259 return 0;
260 }
261
262 struct ath12k_fw_ie {
263 __le32 id;
264 __le32 len;
265 u8 data[];
266 };
267
268 enum ath12k_bd_ie_board_type {
269 ATH12K_BD_IE_BOARD_NAME = 0,
270 ATH12K_BD_IE_BOARD_DATA = 1,
271 };
272
273 enum ath12k_bd_ie_regdb_type {
274 ATH12K_BD_IE_REGDB_NAME = 0,
275 ATH12K_BD_IE_REGDB_DATA = 1,
276 };
277
278 enum ath12k_bd_ie_type {
279 /* contains sub IEs of enum ath12k_bd_ie_board_type */
280 ATH12K_BD_IE_BOARD = 0,
281 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */
282 ATH12K_BD_IE_REGDB = 1,
283 };
284
285 struct ath12k_hw_regs {
286 u32 hal_tcl1_ring_id;
287 u32 hal_tcl1_ring_misc;
288 u32 hal_tcl1_ring_tp_addr_lsb;
289 u32 hal_tcl1_ring_tp_addr_msb;
290 u32 hal_tcl1_ring_consumer_int_setup_ix0;
291 u32 hal_tcl1_ring_consumer_int_setup_ix1;
292 u32 hal_tcl1_ring_msi1_base_lsb;
293 u32 hal_tcl1_ring_msi1_base_msb;
294 u32 hal_tcl1_ring_msi1_data;
295 u32 hal_tcl_ring_base_lsb;
296
297 u32 hal_tcl_status_ring_base_lsb;
298
299 u32 hal_wbm_idle_ring_base_lsb;
300 u32 hal_wbm_idle_ring_misc_addr;
301 u32 hal_wbm_r0_idle_list_cntl_addr;
302 u32 hal_wbm_r0_idle_list_size_addr;
303 u32 hal_wbm_scattered_ring_base_lsb;
304 u32 hal_wbm_scattered_ring_base_msb;
305 u32 hal_wbm_scattered_desc_head_info_ix0;
306 u32 hal_wbm_scattered_desc_head_info_ix1;
307 u32 hal_wbm_scattered_desc_tail_info_ix0;
308 u32 hal_wbm_scattered_desc_tail_info_ix1;
309 u32 hal_wbm_scattered_desc_ptr_hp_addr;
310
311 u32 hal_wbm_sw_release_ring_base_lsb;
312 u32 hal_wbm_sw1_release_ring_base_lsb;
313 u32 hal_wbm0_release_ring_base_lsb;
314 u32 hal_wbm1_release_ring_base_lsb;
315
316 u32 pcie_qserdes_sysclk_en_sel;
317 u32 pcie_pcs_osc_dtct_config_base;
318
319 u32 hal_ppe_rel_ring_base;
320
321 u32 hal_reo2_ring_base;
322 u32 hal_reo1_misc_ctrl_addr;
323 u32 hal_reo1_sw_cookie_cfg0;
324 u32 hal_reo1_sw_cookie_cfg1;
325 u32 hal_reo1_qdesc_lut_base0;
326 u32 hal_reo1_qdesc_lut_base1;
327 u32 hal_reo1_ring_base_lsb;
328 u32 hal_reo1_ring_base_msb;
329 u32 hal_reo1_ring_id;
330 u32 hal_reo1_ring_misc;
331 u32 hal_reo1_ring_hp_addr_lsb;
332 u32 hal_reo1_ring_hp_addr_msb;
333 u32 hal_reo1_ring_producer_int_setup;
334 u32 hal_reo1_ring_msi1_base_lsb;
335 u32 hal_reo1_ring_msi1_base_msb;
336 u32 hal_reo1_ring_msi1_data;
337 u32 hal_reo1_aging_thres_ix0;
338 u32 hal_reo1_aging_thres_ix1;
339 u32 hal_reo1_aging_thres_ix2;
340 u32 hal_reo1_aging_thres_ix3;
341
342 u32 hal_reo2_sw0_ring_base;
343
344 u32 hal_sw2reo_ring_base;
345 u32 hal_sw2reo1_ring_base;
346
347 u32 hal_reo_cmd_ring_base;
348
349 u32 hal_reo_status_ring_base;
350 };
351
ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)352 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)
353 {
354 switch (type) {
355 case ATH12K_BD_IE_BOARD:
356 return "board data";
357 case ATH12K_BD_IE_REGDB:
358 return "regdb data";
359 }
360
361 return "unknown";
362 }
363
364 int ath12k_hw_init(struct ath12k_base *ab);
365
366 #endif
367