1 /*
2 * Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
3 * irq-atmel-aic and irq-atmel-aic5 drivers
4 *
5 * Copyright (C) 2004 SAN People
6 * Copyright (C) 2004 ATMEL
7 * Copyright (C) Rick Bronson
8 * Copyright (C) 2014 Free Electrons
9 *
10 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17 #include <linux/errno.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/slab.h>
24
25 #include "irq-atmel-aic-common.h"
26
27 #define AT91_AIC_PRIOR GENMASK(2, 0)
28 #define AT91_AIC_IRQ_MIN_PRIORITY 0
29 #define AT91_AIC_IRQ_MAX_PRIORITY 7
30
31 #define AT91_AIC_SRCTYPE GENMASK(6, 5)
32 #define AT91_AIC_SRCTYPE_LOW (0 << 5)
33 #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
34 #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
35 #define AT91_AIC_SRCTYPE_RISING (3 << 5)
36
37 struct aic_chip_data {
38 u32 ext_irqs;
39 };
40
aic_common_shutdown(struct irq_data * d)41 static void aic_common_shutdown(struct irq_data *d)
42 {
43 struct irq_chip_type *ct = irq_data_get_chip_type(d);
44
45 ct->chip.irq_mask(d);
46 }
47
aic_common_set_type(struct irq_data * d,unsigned type,unsigned * val)48 int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
49 {
50 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
51 struct aic_chip_data *aic = gc->private;
52 unsigned aic_type;
53
54 switch (type) {
55 case IRQ_TYPE_LEVEL_HIGH:
56 aic_type = AT91_AIC_SRCTYPE_HIGH;
57 break;
58 case IRQ_TYPE_EDGE_RISING:
59 aic_type = AT91_AIC_SRCTYPE_RISING;
60 break;
61 case IRQ_TYPE_LEVEL_LOW:
62 if (!(d->mask & aic->ext_irqs))
63 return -EINVAL;
64
65 aic_type = AT91_AIC_SRCTYPE_LOW;
66 break;
67 case IRQ_TYPE_EDGE_FALLING:
68 if (!(d->mask & aic->ext_irqs))
69 return -EINVAL;
70
71 aic_type = AT91_AIC_SRCTYPE_FALLING;
72 break;
73 default:
74 return -EINVAL;
75 }
76
77 *val &= ~AT91_AIC_SRCTYPE;
78 *val |= aic_type;
79
80 return 0;
81 }
82
aic_common_set_priority(int priority,unsigned * val)83 void aic_common_set_priority(int priority, unsigned *val)
84 {
85 *val &= ~AT91_AIC_PRIOR;
86 *val |= priority;
87 }
88
aic_common_irq_domain_xlate(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)89 int aic_common_irq_domain_xlate(struct irq_domain *d,
90 struct device_node *ctrlr,
91 const u32 *intspec,
92 unsigned int intsize,
93 irq_hw_number_t *out_hwirq,
94 unsigned int *out_type)
95 {
96 if (WARN_ON(intsize < 3))
97 return -EINVAL;
98
99 if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
100 (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
101 return -EINVAL;
102
103 *out_hwirq = intspec[0];
104 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
105
106 return 0;
107 }
108
aic_common_ext_irq_of_init(struct irq_domain * domain)109 static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
110 {
111 struct device_node *node = irq_domain_get_of_node(domain);
112 struct irq_chip_generic *gc;
113 struct aic_chip_data *aic;
114 u32 hwirq;
115
116 gc = irq_get_domain_generic_chip(domain, 0);
117
118 aic = gc->private;
119 aic->ext_irqs |= 1;
120
121 of_property_for_each_u32(node, "atmel,external-irqs", hwirq) {
122 gc = irq_get_domain_generic_chip(domain, hwirq);
123 if (!gc) {
124 pr_warn("AIC: external irq %d >= %d skip it\n",
125 hwirq, domain->revmap_size);
126 continue;
127 }
128
129 aic = gc->private;
130 aic->ext_irqs |= (1 << (hwirq % 32));
131 }
132 }
133
134 #define AT91_RTC_IDR 0x24
135 #define AT91_RTC_IMR 0x28
136 #define AT91_RTC_IRQ_MASK 0x1f
137
aic_common_rtc_irq_fixup(void)138 void __init aic_common_rtc_irq_fixup(void)
139 {
140 struct device_node *np;
141 void __iomem *regs;
142
143 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-rtc");
144 if (!np)
145 np = of_find_compatible_node(NULL, NULL,
146 "atmel,at91sam9x5-rtc");
147
148 if (!np)
149 return;
150
151 regs = of_iomap(np, 0);
152 of_node_put(np);
153
154 if (!regs)
155 return;
156
157 writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
158
159 iounmap(regs);
160 }
161
162 #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
163 #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
164 #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
165
aic_common_rtt_irq_fixup(void)166 void __init aic_common_rtt_irq_fixup(void)
167 {
168 struct device_node *np;
169 void __iomem *regs;
170
171 /*
172 * The at91sam9263 SoC has 2 instances of the RTT block, hence we
173 * iterate over the DT to find each occurrence.
174 */
175 for_each_compatible_node(np, NULL, "atmel,at91sam9260-rtt") {
176 regs = of_iomap(np, 0);
177 if (!regs)
178 continue;
179
180 writel(readl(regs + AT91_RTT_MR) &
181 ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN),
182 regs + AT91_RTT_MR);
183
184 iounmap(regs);
185 }
186 }
187
aic_common_irq_fixup(const struct of_device_id * matches)188 static void __init aic_common_irq_fixup(const struct of_device_id *matches)
189 {
190 struct device_node *root = of_find_node_by_path("/");
191 const struct of_device_id *match;
192
193 if (!root)
194 return;
195
196 match = of_match_node(matches, root);
197
198 if (match) {
199 void (*fixup)(void) = match->data;
200 fixup();
201 }
202
203 of_node_put(root);
204 }
205
aic_common_of_init(struct device_node * node,const struct irq_domain_ops * ops,const char * name,int nirqs,const struct of_device_id * matches)206 struct irq_domain *__init aic_common_of_init(struct device_node *node,
207 const struct irq_domain_ops *ops,
208 const char *name, int nirqs,
209 const struct of_device_id *matches)
210 {
211 struct irq_chip_generic *gc;
212 struct irq_domain *domain;
213 struct aic_chip_data *aic;
214 void __iomem *reg_base;
215 int nchips;
216 int ret;
217 int i;
218
219 nchips = DIV_ROUND_UP(nirqs, 32);
220
221 reg_base = of_iomap(node, 0);
222 if (!reg_base)
223 return ERR_PTR(-ENOMEM);
224
225 aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
226 if (!aic) {
227 ret = -ENOMEM;
228 goto err_iounmap;
229 }
230
231 domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
232 if (!domain) {
233 ret = -ENOMEM;
234 goto err_free_aic;
235 }
236
237 ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
238 handle_fasteoi_irq,
239 IRQ_NOREQUEST | IRQ_NOPROBE |
240 IRQ_NOAUTOEN, 0, 0);
241 if (ret)
242 goto err_domain_remove;
243
244 for (i = 0; i < nchips; i++) {
245 gc = irq_get_domain_generic_chip(domain, i * 32);
246
247 gc->reg_base = reg_base;
248
249 gc->unused = 0;
250 gc->wake_enabled = ~0;
251 gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
252 gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
253 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
254 gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
255 gc->private = &aic[i];
256 }
257
258 aic_common_ext_irq_of_init(domain);
259 aic_common_irq_fixup(matches);
260
261 return domain;
262
263 err_domain_remove:
264 irq_domain_remove(domain);
265
266 err_free_aic:
267 kfree(aic);
268
269 err_iounmap:
270 iounmap(reg_base);
271
272 return ERR_PTR(ret);
273 }
274