1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
5 *
6 * Peter Korsgaard <peter@korsgaard.com>
7 *
8 * Support for the GRLIB port of the controller by
9 * Andreas Larsson <andreas@gaisler.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
21 #include <linux/wait.h>
22 #include <linux/platform_data/i2c-ocores.h>
23 #include <linux/slab.h>
24 #include <linux/io.h>
25 #include <linux/log2.h>
26 #include <linux/spinlock.h>
27 #include <linux/jiffies.h>
28
29 /*
30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
31 * can't run in parallel.
32 */
33 struct ocores_i2c {
34 void __iomem *base;
35 u32 reg_shift;
36 u32 reg_io_width;
37 unsigned long flags;
38 wait_queue_head_t wait;
39 struct i2c_adapter adap;
40 struct i2c_msg *msg;
41 int pos;
42 int nmsgs;
43 int state; /* see STATE_ */
44 spinlock_t process_lock;
45 struct clk *clk;
46 int ip_clock_khz;
47 int bus_clock_khz;
48 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
49 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
50 };
51
52 /* registers */
53 #define OCI2C_PRELOW 0
54 #define OCI2C_PREHIGH 1
55 #define OCI2C_CONTROL 2
56 #define OCI2C_DATA 3
57 #define OCI2C_CMD 4 /* write only */
58 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
59
60 #define OCI2C_CTRL_IEN 0x40
61 #define OCI2C_CTRL_EN 0x80
62
63 #define OCI2C_CMD_START 0x91
64 #define OCI2C_CMD_STOP 0x41
65 #define OCI2C_CMD_READ 0x21
66 #define OCI2C_CMD_WRITE 0x11
67 #define OCI2C_CMD_READ_ACK 0x21
68 #define OCI2C_CMD_READ_NACK 0x29
69 #define OCI2C_CMD_IACK 0x01
70
71 #define OCI2C_STAT_IF 0x01
72 #define OCI2C_STAT_TIP 0x02
73 #define OCI2C_STAT_ARBLOST 0x20
74 #define OCI2C_STAT_BUSY 0x40
75 #define OCI2C_STAT_NACK 0x80
76
77 #define STATE_DONE 0
78 #define STATE_START 1
79 #define STATE_WRITE 2
80 #define STATE_READ 3
81 #define STATE_ERROR 4
82
83 #define TYPE_OCORES 0
84 #define TYPE_GRLIB 1
85
86 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
87
oc_setreg_8(struct ocores_i2c * i2c,int reg,u8 value)88 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
89 {
90 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
91 }
92
oc_setreg_16(struct ocores_i2c * i2c,int reg,u8 value)93 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
94 {
95 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
96 }
97
oc_setreg_32(struct ocores_i2c * i2c,int reg,u8 value)98 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
99 {
100 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
101 }
102
oc_setreg_16be(struct ocores_i2c * i2c,int reg,u8 value)103 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
104 {
105 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
106 }
107
oc_setreg_32be(struct ocores_i2c * i2c,int reg,u8 value)108 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
109 {
110 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
111 }
112
oc_getreg_8(struct ocores_i2c * i2c,int reg)113 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
114 {
115 return ioread8(i2c->base + (reg << i2c->reg_shift));
116 }
117
oc_getreg_16(struct ocores_i2c * i2c,int reg)118 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
119 {
120 return ioread16(i2c->base + (reg << i2c->reg_shift));
121 }
122
oc_getreg_32(struct ocores_i2c * i2c,int reg)123 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
124 {
125 return ioread32(i2c->base + (reg << i2c->reg_shift));
126 }
127
oc_getreg_16be(struct ocores_i2c * i2c,int reg)128 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
129 {
130 return ioread16be(i2c->base + (reg << i2c->reg_shift));
131 }
132
oc_getreg_32be(struct ocores_i2c * i2c,int reg)133 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
134 {
135 return ioread32be(i2c->base + (reg << i2c->reg_shift));
136 }
137
oc_setreg(struct ocores_i2c * i2c,int reg,u8 value)138 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
139 {
140 i2c->setreg(i2c, reg, value);
141 }
142
oc_getreg(struct ocores_i2c * i2c,int reg)143 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
144 {
145 return i2c->getreg(i2c, reg);
146 }
147
ocores_process(struct ocores_i2c * i2c,u8 stat)148 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
149 {
150 struct i2c_msg *msg = i2c->msg;
151 unsigned long flags;
152
153 /*
154 * If we spin here is because we are in timeout, so we are going
155 * to be in STATE_ERROR. See ocores_process_timeout()
156 */
157 spin_lock_irqsave(&i2c->process_lock, flags);
158
159 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
160 /* stop has been sent */
161 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
162 wake_up(&i2c->wait);
163 goto out;
164 }
165
166 /* error? */
167 if (stat & OCI2C_STAT_ARBLOST) {
168 i2c->state = STATE_ERROR;
169 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
170 goto out;
171 }
172
173 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
174 i2c->state =
175 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
176
177 if (stat & OCI2C_STAT_NACK) {
178 i2c->state = STATE_ERROR;
179 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
180 goto out;
181 }
182 } else {
183 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
184 }
185
186 /* end of msg? */
187 if (i2c->pos == msg->len) {
188 i2c->nmsgs--;
189 i2c->msg++;
190 i2c->pos = 0;
191 msg = i2c->msg;
192
193 if (i2c->nmsgs) { /* end? */
194 /* send start? */
195 if (!(msg->flags & I2C_M_NOSTART)) {
196 u8 addr = i2c_8bit_addr_from_msg(msg);
197
198 i2c->state = STATE_START;
199
200 oc_setreg(i2c, OCI2C_DATA, addr);
201 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
202 goto out;
203 }
204 i2c->state = (msg->flags & I2C_M_RD)
205 ? STATE_READ : STATE_WRITE;
206 } else {
207 i2c->state = STATE_DONE;
208 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
209 goto out;
210 }
211 }
212
213 if (i2c->state == STATE_READ) {
214 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
215 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
216 } else {
217 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
218 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
219 }
220
221 out:
222 spin_unlock_irqrestore(&i2c->process_lock, flags);
223 }
224
ocores_isr(int irq,void * dev_id)225 static irqreturn_t ocores_isr(int irq, void *dev_id)
226 {
227 struct ocores_i2c *i2c = dev_id;
228 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
229
230 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
231 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
232 return IRQ_NONE;
233 } else if (!(stat & OCI2C_STAT_IF)) {
234 return IRQ_NONE;
235 }
236 ocores_process(i2c, stat);
237
238 return IRQ_HANDLED;
239 }
240
241 /**
242 * ocores_process_timeout() - Process timeout event
243 * @i2c: ocores I2C device instance
244 */
ocores_process_timeout(struct ocores_i2c * i2c)245 static void ocores_process_timeout(struct ocores_i2c *i2c)
246 {
247 unsigned long flags;
248
249 spin_lock_irqsave(&i2c->process_lock, flags);
250 i2c->state = STATE_ERROR;
251 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
252 spin_unlock_irqrestore(&i2c->process_lock, flags);
253 }
254
255 /**
256 * ocores_wait() - Wait until something change in a given register
257 * @i2c: ocores I2C device instance
258 * @reg: register to query
259 * @mask: bitmask to apply on register value
260 * @val: expected result
261 * @timeout: timeout in jiffies
262 *
263 * Timeout is necessary to avoid to stay here forever when the chip
264 * does not answer correctly.
265 *
266 * Return: 0 on success, -ETIMEDOUT on timeout
267 */
ocores_wait(struct ocores_i2c * i2c,int reg,u8 mask,u8 val,const unsigned long timeout)268 static int ocores_wait(struct ocores_i2c *i2c,
269 int reg, u8 mask, u8 val,
270 const unsigned long timeout)
271 {
272 unsigned long j;
273
274 j = jiffies + timeout;
275 while (1) {
276 u8 status = oc_getreg(i2c, reg);
277
278 if ((status & mask) == val)
279 break;
280
281 if (time_after(jiffies, j))
282 return -ETIMEDOUT;
283 }
284 return 0;
285 }
286
287 /**
288 * ocores_poll_wait() - Wait until is possible to process some data
289 * @i2c: ocores I2C device instance
290 *
291 * Used when the device is in polling mode (interrupts disabled).
292 *
293 * Return: 0 on success, -ETIMEDOUT on timeout
294 */
ocores_poll_wait(struct ocores_i2c * i2c)295 static int ocores_poll_wait(struct ocores_i2c *i2c)
296 {
297 u8 mask;
298 int err;
299
300 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
301 /* transfer is over */
302 mask = OCI2C_STAT_BUSY;
303 } else {
304 /* on going transfer */
305 mask = OCI2C_STAT_TIP;
306 /*
307 * We wait for the data to be transferred (8bit),
308 * then we start polling on the ACK/NACK bit
309 */
310 udelay((8 * 1000) / i2c->bus_clock_khz);
311 }
312
313 /*
314 * once we are here we expect to get the expected result immediately
315 * so if after 1ms we timeout then something is broken.
316 */
317 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
318 if (err)
319 dev_warn(i2c->adap.dev.parent,
320 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
321 __func__, mask);
322 return err;
323 }
324
325 /**
326 * ocores_process_polling() - It handles an IRQ-less transfer
327 * @i2c: ocores I2C device instance
328 *
329 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
330 * (only that IRQ are not produced). This means that we can re-use entirely
331 * ocores_isr(), we just add our polling code around it.
332 *
333 * It can run in atomic context
334 *
335 * Return: 0 on success, -ETIMEDOUT on timeout
336 */
ocores_process_polling(struct ocores_i2c * i2c)337 static int ocores_process_polling(struct ocores_i2c *i2c)
338 {
339 irqreturn_t ret;
340 int err = 0;
341
342 while (1) {
343 err = ocores_poll_wait(i2c);
344 if (err)
345 break; /* timeout */
346
347 ret = ocores_isr(-1, i2c);
348 if (ret == IRQ_NONE)
349 break; /* all messages have been transferred */
350 else {
351 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
352 if (i2c->state == STATE_DONE)
353 break;
354 }
355 }
356
357 return err;
358 }
359
ocores_xfer_core(struct ocores_i2c * i2c,struct i2c_msg * msgs,int num,bool polling)360 static int ocores_xfer_core(struct ocores_i2c *i2c,
361 struct i2c_msg *msgs, int num,
362 bool polling)
363 {
364 int ret = 0;
365 u8 ctrl;
366
367 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
368 if (polling)
369 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
370 else
371 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
372
373 i2c->msg = msgs;
374 i2c->pos = 0;
375 i2c->nmsgs = num;
376 i2c->state = STATE_START;
377
378 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
379 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
380
381 if (polling) {
382 ret = ocores_process_polling(i2c);
383 } else {
384 if (wait_event_timeout(i2c->wait,
385 (i2c->state == STATE_ERROR) ||
386 (i2c->state == STATE_DONE), HZ) == 0)
387 ret = -ETIMEDOUT;
388 }
389 if (ret) {
390 ocores_process_timeout(i2c);
391 return ret;
392 }
393
394 return (i2c->state == STATE_DONE) ? num : -EIO;
395 }
396
ocores_xfer_polling(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)397 static int ocores_xfer_polling(struct i2c_adapter *adap,
398 struct i2c_msg *msgs, int num)
399 {
400 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
401 }
402
ocores_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)403 static int ocores_xfer(struct i2c_adapter *adap,
404 struct i2c_msg *msgs, int num)
405 {
406 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
407 }
408
ocores_init(struct device * dev,struct ocores_i2c * i2c)409 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
410 {
411 int prescale;
412 int diff;
413 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
414
415 /* make sure the device is disabled */
416 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
417 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
418
419 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
420 prescale = clamp(prescale, 0, 0xffff);
421
422 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
423 if (abs(diff) > i2c->bus_clock_khz / 10) {
424 dev_err(dev,
425 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
426 i2c->ip_clock_khz, i2c->bus_clock_khz);
427 return -EINVAL;
428 }
429
430 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
431 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
432
433 /* Init the device */
434 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
435 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
436
437 return 0;
438 }
439
440
ocores_func(struct i2c_adapter * adap)441 static u32 ocores_func(struct i2c_adapter *adap)
442 {
443 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
444 }
445
446 static struct i2c_algorithm ocores_algorithm = {
447 .xfer = ocores_xfer,
448 .xfer_atomic = ocores_xfer_polling,
449 .functionality = ocores_func,
450 };
451
452 static const struct i2c_adapter ocores_adapter = {
453 .owner = THIS_MODULE,
454 .name = "i2c-ocores",
455 .class = I2C_CLASS_DEPRECATED,
456 .algo = &ocores_algorithm,
457 };
458
459 static const struct of_device_id ocores_i2c_match[] = {
460 {
461 .compatible = "opencores,i2c-ocores",
462 .data = (void *)TYPE_OCORES,
463 },
464 {
465 .compatible = "aeroflexgaisler,i2cmst",
466 .data = (void *)TYPE_GRLIB,
467 },
468 {
469 .compatible = "sifive,fu540-c000-i2c",
470 },
471 {
472 .compatible = "sifive,i2c0",
473 },
474 {},
475 };
476 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
477
478 #ifdef CONFIG_OF
479 /*
480 * Read and write functions for the GRLIB port of the controller. Registers are
481 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
482 * register. The subsequent registers have their offsets decreased accordingly.
483 */
oc_getreg_grlib(struct ocores_i2c * i2c,int reg)484 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
485 {
486 u32 rd;
487 int rreg = reg;
488
489 if (reg != OCI2C_PRELOW)
490 rreg--;
491 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
492 if (reg == OCI2C_PREHIGH)
493 return (u8)(rd >> 8);
494 else
495 return (u8)rd;
496 }
497
oc_setreg_grlib(struct ocores_i2c * i2c,int reg,u8 value)498 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
499 {
500 u32 curr, wr;
501 int rreg = reg;
502
503 if (reg != OCI2C_PRELOW)
504 rreg--;
505 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
506 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
507 if (reg == OCI2C_PRELOW)
508 wr = (curr & 0xff00) | value;
509 else
510 wr = (((u32)value) << 8) | (curr & 0xff);
511 } else {
512 wr = value;
513 }
514 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
515 }
516
ocores_i2c_of_probe(struct platform_device * pdev,struct ocores_i2c * i2c)517 static int ocores_i2c_of_probe(struct platform_device *pdev,
518 struct ocores_i2c *i2c)
519 {
520 struct device_node *np = pdev->dev.of_node;
521 const struct of_device_id *match;
522 u32 val;
523 u32 clock_frequency;
524 bool clock_frequency_present;
525
526 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
527 /* no 'reg-shift', check for deprecated 'regstep' */
528 if (!of_property_read_u32(np, "regstep", &val)) {
529 if (!is_power_of_2(val)) {
530 dev_err(&pdev->dev, "invalid regstep %d\n",
531 val);
532 return -EINVAL;
533 }
534 i2c->reg_shift = ilog2(val);
535 dev_warn(&pdev->dev,
536 "regstep property deprecated, use reg-shift\n");
537 }
538 }
539
540 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
541 &clock_frequency);
542 i2c->bus_clock_khz = 100;
543
544 i2c->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
545 if (IS_ERR(i2c->clk))
546 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
547 "devm_clk_get_optional_enabled failed\n");
548
549 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
550 if (clock_frequency_present)
551 i2c->bus_clock_khz = clock_frequency / 1000;
552 if (i2c->ip_clock_khz == 0) {
553 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
554 &val)) {
555 if (!clock_frequency_present) {
556 dev_err(&pdev->dev,
557 "Missing required parameter 'opencores,ip-clock-frequency'\n");
558 return -ENODEV;
559 }
560 i2c->ip_clock_khz = clock_frequency / 1000;
561 dev_warn(&pdev->dev,
562 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
563 } else {
564 i2c->ip_clock_khz = val / 1000;
565 if (clock_frequency_present)
566 i2c->bus_clock_khz = clock_frequency / 1000;
567 }
568 }
569
570 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
571 &i2c->reg_io_width);
572
573 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
574 if (match && (long)match->data == TYPE_GRLIB) {
575 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
576 i2c->setreg = oc_setreg_grlib;
577 i2c->getreg = oc_getreg_grlib;
578 }
579
580 return 0;
581 }
582 #else
583 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
584 #endif
585
ocores_i2c_probe(struct platform_device * pdev)586 static int ocores_i2c_probe(struct platform_device *pdev)
587 {
588 struct ocores_i2c *i2c;
589 struct ocores_i2c_platform_data *pdata;
590 struct resource *res;
591 int irq;
592 int ret;
593 int i;
594
595 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
596 if (!i2c)
597 return -ENOMEM;
598
599 spin_lock_init(&i2c->process_lock);
600
601 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
602 if (res) {
603 i2c->base = devm_ioremap_resource(&pdev->dev, res);
604 if (IS_ERR(i2c->base))
605 return PTR_ERR(i2c->base);
606 } else {
607 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
608 if (!res)
609 return -EINVAL;
610 if (!devm_request_region(&pdev->dev, res->start,
611 resource_size(res),
612 pdev->name)) {
613 dev_err(&pdev->dev, "Can't get I/O resource.\n");
614 return -EBUSY;
615 }
616 i2c->base = devm_ioport_map(&pdev->dev, res->start,
617 resource_size(res));
618 if (!i2c->base) {
619 dev_err(&pdev->dev, "Can't map I/O resource.\n");
620 return -EBUSY;
621 }
622 i2c->reg_io_width = 1;
623 }
624
625 pdata = dev_get_platdata(&pdev->dev);
626 if (pdata) {
627 i2c->reg_shift = pdata->reg_shift;
628 i2c->reg_io_width = pdata->reg_io_width;
629 i2c->ip_clock_khz = pdata->clock_khz;
630 if (pdata->bus_khz)
631 i2c->bus_clock_khz = pdata->bus_khz;
632 else
633 i2c->bus_clock_khz = 100;
634 } else {
635 ret = ocores_i2c_of_probe(pdev, i2c);
636 if (ret)
637 return ret;
638 }
639
640 if (i2c->reg_io_width == 0)
641 i2c->reg_io_width = 1; /* Set to default value */
642
643 if (!i2c->setreg || !i2c->getreg) {
644 bool be = pdata ? pdata->big_endian :
645 of_device_is_big_endian(pdev->dev.of_node);
646
647 switch (i2c->reg_io_width) {
648 case 1:
649 i2c->setreg = oc_setreg_8;
650 i2c->getreg = oc_getreg_8;
651 break;
652
653 case 2:
654 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
655 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
656 break;
657
658 case 4:
659 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
660 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
661 break;
662
663 default:
664 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
665 i2c->reg_io_width);
666 return -EINVAL;
667 }
668 }
669
670 init_waitqueue_head(&i2c->wait);
671
672 irq = platform_get_irq_optional(pdev, 0);
673 /*
674 * Since the SoC does have an interrupt, its DT has an interrupt
675 * property - But this should be bypassed as the IRQ logic in this
676 * SoC is broken.
677 */
678 if (of_device_is_compatible(pdev->dev.of_node,
679 "sifive,fu540-c000-i2c")) {
680 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
681 irq = -ENXIO;
682 }
683
684 if (irq == -ENXIO) {
685 ocores_algorithm.xfer = ocores_xfer_polling;
686 } else {
687 if (irq < 0)
688 return irq;
689 }
690
691 if (ocores_algorithm.xfer != ocores_xfer_polling) {
692 ret = devm_request_any_context_irq(&pdev->dev, irq,
693 ocores_isr, 0,
694 pdev->name, i2c);
695 if (ret) {
696 dev_err(&pdev->dev, "Cannot claim IRQ\n");
697 return ret;
698 }
699 }
700
701 ret = ocores_init(&pdev->dev, i2c);
702 if (ret)
703 return ret;
704
705 /* hook up driver to tree */
706 platform_set_drvdata(pdev, i2c);
707 i2c->adap = ocores_adapter;
708 i2c_set_adapdata(&i2c->adap, i2c);
709 i2c->adap.dev.parent = &pdev->dev;
710 i2c->adap.dev.of_node = pdev->dev.of_node;
711
712 /* add i2c adapter to i2c tree */
713 ret = i2c_add_adapter(&i2c->adap);
714 if (ret)
715 return ret;
716
717 /* add in known devices to the bus */
718 if (pdata) {
719 for (i = 0; i < pdata->num_devices; i++)
720 i2c_new_client_device(&i2c->adap, pdata->devices + i);
721 }
722
723 return 0;
724 }
725
ocores_i2c_remove(struct platform_device * pdev)726 static void ocores_i2c_remove(struct platform_device *pdev)
727 {
728 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
729 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
730
731 /* disable i2c logic */
732 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
733 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
734
735 /* remove adapter & data */
736 i2c_del_adapter(&i2c->adap);
737 }
738
ocores_i2c_suspend(struct device * dev)739 static int ocores_i2c_suspend(struct device *dev)
740 {
741 struct ocores_i2c *i2c = dev_get_drvdata(dev);
742 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
743
744 /* make sure the device is disabled */
745 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
746 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
747
748 clk_disable_unprepare(i2c->clk);
749 return 0;
750 }
751
ocores_i2c_resume(struct device * dev)752 static int ocores_i2c_resume(struct device *dev)
753 {
754 struct ocores_i2c *i2c = dev_get_drvdata(dev);
755 unsigned long rate;
756 int ret;
757
758 ret = clk_prepare_enable(i2c->clk);
759 if (ret)
760 return dev_err_probe(dev, ret, "clk_prepare_enable failed\n");
761 rate = clk_get_rate(i2c->clk) / 1000;
762 if (rate)
763 i2c->ip_clock_khz = rate;
764 return ocores_init(dev, i2c);
765 }
766
767 static DEFINE_NOIRQ_DEV_PM_OPS(ocores_i2c_pm,
768 ocores_i2c_suspend, ocores_i2c_resume);
769
770 static struct platform_driver ocores_i2c_driver = {
771 .probe = ocores_i2c_probe,
772 .remove_new = ocores_i2c_remove,
773 .driver = {
774 .name = "ocores-i2c",
775 .of_match_table = ocores_i2c_match,
776 .pm = pm_sleep_ptr(&ocores_i2c_pm),
777 },
778 };
779
780 module_platform_driver(ocores_i2c_driver);
781
782 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
783 MODULE_DESCRIPTION("OpenCores I2C bus driver");
784 MODULE_LICENSE("GPL");
785 MODULE_ALIAS("platform:ocores-i2c");
786