1 #ifndef __src_nvidia_generated_g_rpc_structures_h__
2 #define __src_nvidia_generated_g_rpc_structures_h__
3 #include <nvrm/535.113.01/nvidia/generated/g_sdk-structures.h>
4 #include <nvrm/535.113.01/nvidia/kernel/inc/vgpu/sdk-structures.h>
5 
6 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
7 
8 /*
9  * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
10  * SPDX-License-Identifier: MIT
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice shall be included in
20  * all copies or substantial portions of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28  * DEALINGS IN THE SOFTWARE.
29  */
30 
31 typedef struct rpc_alloc_memory_v13_01
32 {
33     NvHandle   hClient;
34     NvHandle   hDevice;
35     NvHandle   hMemory;
36     NvU32      hClass;
37     NvU32      flags;
38     NvU32      pteAdjust;
39     NvU32      format;
40     NvU64      length NV_ALIGN_BYTES(8);
41     NvU32      pageCount;
42     struct pte_desc pteDesc;
43 } rpc_alloc_memory_v13_01;
44 
45 typedef struct rpc_free_v03_00
46 {
47     NVOS00_PARAMETERS_v03_00 params;
48 } rpc_free_v03_00;
49 
50 typedef struct rpc_unloading_guest_driver_v1F_07
51 {
52     NvBool     bInPMTransition;
53     NvBool     bGc6Entering;
54     NvU32      newLevel;
55 } rpc_unloading_guest_driver_v1F_07;
56 
57 typedef struct rpc_update_bar_pde_v15_00
58 {
59     UpdateBarPde_v15_00 info;
60 } rpc_update_bar_pde_v15_00;
61 
62 typedef struct rpc_gsp_rm_alloc_v03_00
63 {
64     NvHandle   hClient;
65     NvHandle   hParent;
66     NvHandle   hObject;
67     NvU32      hClass;
68     NvU32      status;
69     NvU32      paramsSize;
70     NvU32      flags;
71     NvU8       reserved[4];
72     NvU8       params[];
73 } rpc_gsp_rm_alloc_v03_00;
74 
75 typedef struct rpc_gsp_rm_control_v03_00
76 {
77     NvHandle   hClient;
78     NvHandle   hObject;
79     NvU32      cmd;
80     NvU32      status;
81     NvU32      paramsSize;
82     NvU32      flags;
83     NvU8       params[];
84 } rpc_gsp_rm_control_v03_00;
85 
86 typedef struct rpc_run_cpu_sequencer_v17_00
87 {
88     NvU32      bufferSizeDWord;
89     NvU32      cmdIndex;
90     NvU32      regSaveArea[8];
91     NvU32      commandBuffer[];
92 } rpc_run_cpu_sequencer_v17_00;
93 
94 typedef struct rpc_post_event_v17_00
95 {
96     NvHandle   hClient;
97     NvHandle   hEvent;
98     NvU32      notifyIndex;
99     NvU32      data;
100     NvU16      info16;
101     NvU32      status;
102     NvU32      eventDataSize;
103     NvBool     bNotifyList;
104     NvU8       eventData[];
105 } rpc_post_event_v17_00;
106 
107 typedef struct rpc_rc_triggered_v17_02
108 {
109     NvU32      nv2080EngineType;
110     NvU32      chid;
111     NvU32      exceptType;
112     NvU32      scope;
113     NvU16      partitionAttributionId;
114 } rpc_rc_triggered_v17_02;
115 
116 typedef struct rpc_os_error_log_v17_00
117 {
118     NvU32      exceptType;
119     NvU32      runlistId;
120     NvU32      chid;
121     char       errString[0x100];
122 } rpc_os_error_log_v17_00;
123 
124 #endif
125