1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __SKL_WATERMARK_H__ 7 #define __SKL_WATERMARK_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_global_state.h" 13 #include "intel_wm_types.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_bw_state; 18 struct intel_crtc; 19 struct intel_crtc_state; 20 struct intel_plane; 21 struct skl_pipe_wm; 22 struct skl_wm_level; 23 24 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); 25 26 void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 27 void intel_sagv_post_plane_update(struct intel_atomic_state *state); 28 bool intel_can_enable_sagv(struct drm_i915_private *i915, 29 const struct intel_bw_state *bw_state); 30 bool intel_has_sagv(struct drm_i915_private *i915); 31 32 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 33 const struct skl_ddb_entry *entry); 34 35 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 36 const struct skl_ddb_entry *entries, 37 int num_entries, int ignore_idx); 38 39 void intel_wm_state_verify(struct intel_atomic_state *state, 40 struct intel_crtc *crtc); 41 42 void skl_watermark_ipc_init(struct drm_i915_private *i915); 43 void skl_watermark_ipc_update(struct drm_i915_private *i915); 44 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); 45 void skl_watermark_debugfs_register(struct drm_i915_private *i915); 46 47 unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, 48 int initial_wm_level); 49 void skl_wm_init(struct drm_i915_private *i915); 50 51 const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 52 enum plane_id plane_id, 53 int level); 54 const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 55 enum plane_id plane_id); 56 57 struct intel_dbuf_state { 58 struct intel_global_state base; 59 60 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 61 unsigned int weight[I915_MAX_PIPES]; 62 u8 slices[I915_MAX_PIPES]; 63 u8 enabled_slices; 64 u8 active_pipes; 65 u8 mdclk_cdclk_ratio; 66 bool joined_mbus; 67 }; 68 69 struct intel_dbuf_state * 70 intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 71 72 #define to_intel_dbuf_state(global_state) \ 73 container_of_const((global_state), struct intel_dbuf_state, base) 74 75 #define intel_atomic_get_old_dbuf_state(state) \ 76 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 77 #define intel_atomic_get_new_dbuf_state(state) \ 78 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 79 80 int intel_dbuf_init(struct drm_i915_private *i915); 81 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 82 int ratio); 83 84 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 85 void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 86 void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, 87 int ratio, bool joined_mbus); 88 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); 89 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); 90 91 #endif /* __SKL_WATERMARK_H__ */ 92 93