1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_de.h"
9 #include "intel_display_wa.h"
10
gen11_display_wa_apply(struct drm_i915_private * i915)11 static void gen11_display_wa_apply(struct drm_i915_private *i915)
12 {
13 /* Wa_14010594013 */
14 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
15 }
16
xe_d_display_wa_apply(struct drm_i915_private * i915)17 static void xe_d_display_wa_apply(struct drm_i915_private *i915)
18 {
19 /* Wa_14013723622 */
20 intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
21 }
22
adlp_display_wa_apply(struct drm_i915_private * i915)23 static void adlp_display_wa_apply(struct drm_i915_private *i915)
24 {
25 /* Wa_22011091694:adlp */
26 intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
27
28 /* Bspec/49189 Initialize Sequence */
29 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
30 }
31
intel_display_wa_apply(struct drm_i915_private * i915)32 void intel_display_wa_apply(struct drm_i915_private *i915)
33 {
34 if (IS_ALDERLAKE_P(i915))
35 adlp_display_wa_apply(i915);
36 else if (DISPLAY_VER(i915) == 12)
37 xe_d_display_wa_apply(i915);
38 else if (DISPLAY_VER(i915) == 11)
39 gen11_display_wa_apply(i915);
40 }
41