1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2023 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #ifndef __DCN35_OPP_H
28 #define __DCN35_OPP_H
29 
30 #include "dcn20/dcn20_opp.h"
31 
32 #define OPP_REG_VARIABLE_LIST_DCN3_5  \
33 	OPP_REG_VARIABLE_LIST_DCN2_0; \
34 	uint32_t OPP_TOP_CLK_CONTROL
35 
36 #define OPP_MASK_SH_LIST_DCN35(mask_sh)  \
37 	OPP_MASK_SH_LIST_DCN20(mask_sh), \
38 		OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh)
39 
40 #define OPP_DCN35_REG_FIELD_LIST(type)          \
41 	struct {                                \
42 		OPP_DCN20_REG_FIELD_LIST(type); \
43 		type OPP_FGCG_REP_DIS;          \
44 	}
45 
46 struct dcn35_opp_registers {
47 	OPP_REG_VARIABLE_LIST_DCN3_5;
48 };
49 
50 struct dcn35_opp_shift {
51 	OPP_DCN35_REG_FIELD_LIST(uint8_t);
52 };
53 
54 struct dcn35_opp_mask {
55 	OPP_DCN35_REG_FIELD_LIST(uint32_t);
56 };
57 
58 void dcn35_opp_construct(struct dcn20_opp *oppn20,
59 	struct dc_context *ctx,
60 	uint32_t inst,
61 	const struct dcn35_opp_registers *regs,
62 	const struct dcn35_opp_shift *opp_shift,
63 	const struct dcn35_opp_mask *opp_mask);
64 
65 void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);
66 
67 #endif
68