1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce110/dce110_hwseq.h"
27 #include "dcn10/dcn10_hwseq.h"
28 #include "dcn20/dcn20_hwseq.h"
29 #include "dcn21/dcn21_hwseq.h"
30 #include "dcn30/dcn30_hwseq.h"
31 #include "dcn31/dcn31_hwseq.h"
32 #include "dcn32/dcn32_hwseq.h"
33 #include "dcn401/dcn401_hwseq.h"
34 #include "dcn32_init.h"
35
36 static const struct hw_sequencer_funcs dcn32_funcs = {
37 .program_gamut_remap = dcn30_program_gamut_remap,
38 .init_hw = dcn32_init_hw,
39 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
40 .apply_ctx_for_surface = NULL,
41 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
42 .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
43 .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
44 .update_plane_addr = dcn20_update_plane_addr,
45 .update_dchub = dcn10_update_dchub,
46 .update_pending_status = dcn10_update_pending_status,
47 .program_output_csc = dcn20_program_output_csc,
48 .enable_accelerated_mode = dce110_enable_accelerated_mode,
49 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
50 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
51 .update_info_frame = dcn31_update_info_frame,
52 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
53 .enable_stream = dcn20_enable_stream,
54 .disable_stream = dce110_disable_stream,
55 .unblank_stream = dcn32_unblank_stream,
56 .blank_stream = dce110_blank_stream,
57 .enable_audio_stream = dce110_enable_audio_stream,
58 .disable_audio_stream = dce110_disable_audio_stream,
59 .disable_plane = dcn20_disable_plane,
60 .disable_pixel_data = dcn20_disable_pixel_data,
61 .pipe_control_lock = dcn20_pipe_control_lock,
62 .interdependent_update_lock = dcn32_interdependent_update_lock,
63 .cursor_lock = dcn10_cursor_lock,
64 .prepare_bandwidth = dcn32_prepare_bandwidth,
65 .optimize_bandwidth = dcn20_optimize_bandwidth,
66 .update_bandwidth = dcn20_update_bandwidth,
67 .set_drr = dcn10_set_drr,
68 .get_position = dcn10_get_position,
69 .set_static_screen_control = dcn31_set_static_screen_control,
70 .setup_stereo = dcn10_setup_stereo,
71 .set_avmute = dcn30_set_avmute,
72 .log_hw_state = dcn10_log_hw_state,
73 .get_hw_state = dcn10_get_hw_state,
74 .clear_status_bits = dcn10_clear_status_bits,
75 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
76 .edp_backlight_control = dce110_edp_backlight_control,
77 .edp_power_control = dce110_edp_power_control,
78 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
79 .edp_wait_for_T12 = dce110_edp_wait_for_T12,
80 .set_cursor_position = dcn10_set_cursor_position,
81 .set_cursor_attribute = dcn10_set_cursor_attribute,
82 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
83 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
84 .set_clock = dcn10_set_clock,
85 .get_clock = dcn10_get_clock,
86 .program_triplebuffer = dcn20_program_triple_buffer,
87 .enable_writeback = dcn30_enable_writeback,
88 .disable_writeback = dcn30_disable_writeback,
89 .update_writeback = dcn30_update_writeback,
90 .mmhubbub_warmup = dcn30_mmhubbub_warmup,
91 .dmdata_status_done = dcn20_dmdata_status_done,
92 .program_dmdata_engine = dcn30_program_dmdata_engine,
93 .set_dmdata_attributes = dcn20_set_dmdata_attributes,
94 .init_sys_ctx = dcn20_init_sys_ctx,
95 .init_vm_ctx = dcn20_init_vm_ctx,
96 .set_flip_control_gsl = dcn20_set_flip_control_gsl,
97 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
98 .calc_vupdate_position = dcn10_calc_vupdate_position,
99 .apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
100 .does_plane_fit_in_mall = NULL,
101 .set_backlight_level = dcn21_set_backlight_level,
102 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
103 .hardware_release = dcn30_hardware_release,
104 .set_pipe = dcn21_set_pipe,
105 .enable_lvds_link_output = dce110_enable_lvds_link_output,
106 .enable_tmds_link_output = dce110_enable_tmds_link_output,
107 .enable_dp_link_output = dce110_enable_dp_link_output,
108 .disable_link_output = dcn32_disable_link_output,
109 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
110 .get_dcc_en_bits = dcn10_get_dcc_en_bits,
111 .commit_subvp_config = dcn32_commit_subvp_config,
112 .enable_phantom_streams = dcn32_enable_phantom_streams,
113 .disable_phantom_streams = dcn32_disable_phantom_streams,
114 .subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
115 .update_visual_confirm_color = dcn10_update_visual_confirm_color,
116 .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast,
117 .update_phantom_vp_position = dcn32_update_phantom_vp_position,
118 .update_dsc_pg = dcn32_update_dsc_pg,
119 .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,
120 .blank_phantom = dcn32_blank_phantom,
121 .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,
122 .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,
123 .program_outstanding_updates = dcn32_program_outstanding_updates,
124 };
125
126 static const struct hwseq_private_funcs dcn32_private_funcs = {
127 .init_pipes = dcn10_init_pipes,
128 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
129 .update_mpcc = dcn20_update_mpcc,
130 .set_input_transfer_func = dcn32_set_input_transfer_func,
131 .set_output_transfer_func = dcn32_set_output_transfer_func,
132 .power_down = dce110_power_down,
133 .enable_display_power_gating = dcn10_dummy_display_power_gating,
134 .blank_pixel_data = dcn20_blank_pixel_data,
135 .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
136 .enable_stream_timing = dcn20_enable_stream_timing,
137 .edp_backlight_control = dce110_edp_backlight_control,
138 .disable_stream_gating = dcn20_disable_stream_gating,
139 .enable_stream_gating = dcn20_enable_stream_gating,
140 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
141 .did_underflow_occur = dcn10_did_underflow_occur,
142 .init_blank = dcn32_init_blank,
143 .disable_vga = dcn20_disable_vga,
144 .bios_golden_init = dcn10_bios_golden_init,
145 .plane_atomic_disable = dcn20_plane_atomic_disable,
146 .plane_atomic_power_down = dcn10_plane_atomic_power_down,
147 .enable_power_gating_plane = dcn32_enable_power_gating_plane,
148 .hubp_pg_control = dcn32_hubp_pg_control,
149 .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
150 .update_odm = dcn32_update_odm,
151 .dsc_pg_control = dcn32_dsc_pg_control,
152 .dsc_pg_status = dcn32_dsc_pg_status,
153 .set_hdr_multiplier = dcn10_set_hdr_multiplier,
154 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
155 .wait_for_blank_complete = dcn20_wait_for_blank_complete,
156 .dccg_init = dcn20_dccg_init,
157 .set_mcm_luts = dcn32_set_mcm_luts,
158 .program_mall_pipe_config = dcn32_program_mall_pipe_config,
159 .update_force_pstate = dcn32_update_force_pstate,
160 .update_mall_sel = dcn32_update_mall_sel,
161 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
162 .resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,
163 .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
164 .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
165 .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,
166 };
167
dcn32_hw_sequencer_init_functions(struct dc * dc)168 void dcn32_hw_sequencer_init_functions(struct dc *dc)
169 {
170 dc->hwss = dcn32_funcs;
171 dc->hwseq->funcs = dcn32_private_funcs;
172
173 }
174