1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dc_bios_types.h"
28 #include "dcn30/dcn30_dio_stream_encoder.h"
29 #include "dcn32_dio_stream_encoder.h"
30 #include "reg_helper.h"
31 #include "hw_shared.h"
32 #include "link.h"
33 #include "dpcd_defs.h"
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48 #define CTX \
49 enc1->base.ctx
50
51
52
enc32_dp_set_odm_combine(struct stream_encoder * enc,bool two_pixel_per_cyle)53 static void enc32_dp_set_odm_combine(
54 struct stream_encoder *enc,
55 bool two_pixel_per_cyle)
56 {
57 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
58
59 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, two_pixel_per_cyle ? 1 : 0);
60 }
61
62 /* setup stream encoder in dvi mode */
enc32_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)63 static void enc32_stream_encoder_dvi_set_stream_attribute(
64 struct stream_encoder *enc,
65 struct dc_crtc_timing *crtc_timing,
66 bool is_dual_link)
67 {
68 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
69
70 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
71 struct bp_encoder_control cntl = {0};
72
73 cntl.action = ENCODER_CONTROL_SETUP;
74 cntl.engine_id = enc1->base.id;
75 cntl.signal = is_dual_link ?
76 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
77 cntl.enable_dp_audio = false;
78 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
79 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
80
81 if (enc1->base.bp->funcs->encoder_control(
82 enc1->base.bp, &cntl) != BP_RESULT_OK)
83 return;
84
85 } else {
86
87 //Set pattern for clock channel, default vlue 0x63 does not work
88 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
89
90 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
91
92 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
93
94 /* DIG_START is removed from the register spec */
95 }
96
97 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
98 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
99 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
100 }
101
102 /* setup stream encoder in hdmi mode */
enc32_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)103 static void enc32_stream_encoder_hdmi_set_stream_attribute(
104 struct stream_encoder *enc,
105 struct dc_crtc_timing *crtc_timing,
106 int actual_pix_clk_khz,
107 bool enable_audio)
108 {
109 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
110
111 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
112 struct bp_encoder_control cntl = {0};
113
114 cntl.action = ENCODER_CONTROL_SETUP;
115 cntl.engine_id = enc1->base.id;
116 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
117 cntl.enable_dp_audio = enable_audio;
118 cntl.pixel_clock = actual_pix_clk_khz;
119 cntl.lanes_number = LANE_COUNT_FOUR;
120
121 if (enc1->base.bp->funcs->encoder_control(
122 enc1->base.bp, &cntl) != BP_RESULT_OK)
123 return;
124
125 } else {
126
127 //Set pattern for clock channel, default vlue 0x63 does not work
128 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
129
130 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
131
132 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
133
134 /* DIG_START is removed from the register spec */
135 }
136
137 /* Configure pixel encoding */
138 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
139
140 /* setup HDMI engine */
141 REG_UPDATE_6(HDMI_CONTROL,
142 HDMI_PACKET_GEN_VERSION, 1,
143 HDMI_KEEPOUT_MODE, 1,
144 HDMI_DEEP_COLOR_ENABLE, 0,
145 HDMI_DATA_SCRAMBLE_EN, 0,
146 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
147 HDMI_CLOCK_CHANNEL_RATE, 0);
148
149 /* Configure color depth */
150 switch (crtc_timing->display_color_depth) {
151 case COLOR_DEPTH_888:
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
153 break;
154 case COLOR_DEPTH_101010:
155 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
156 REG_UPDATE_2(HDMI_CONTROL,
157 HDMI_DEEP_COLOR_DEPTH, 1,
158 HDMI_DEEP_COLOR_ENABLE, 0);
159 } else {
160 REG_UPDATE_2(HDMI_CONTROL,
161 HDMI_DEEP_COLOR_DEPTH, 1,
162 HDMI_DEEP_COLOR_ENABLE, 1);
163 }
164 break;
165 case COLOR_DEPTH_121212:
166 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
167 REG_UPDATE_2(HDMI_CONTROL,
168 HDMI_DEEP_COLOR_DEPTH, 2,
169 HDMI_DEEP_COLOR_ENABLE, 0);
170 } else {
171 REG_UPDATE_2(HDMI_CONTROL,
172 HDMI_DEEP_COLOR_DEPTH, 2,
173 HDMI_DEEP_COLOR_ENABLE, 1);
174 }
175 break;
176 case COLOR_DEPTH_161616:
177 REG_UPDATE_2(HDMI_CONTROL,
178 HDMI_DEEP_COLOR_DEPTH, 3,
179 HDMI_DEEP_COLOR_ENABLE, 1);
180 break;
181 default:
182 break;
183 }
184
185 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
186 /* enable HDMI data scrambler
187 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
188 * Clock channel frequency is 1/4 of character rate.
189 */
190 REG_UPDATE_2(HDMI_CONTROL,
191 HDMI_DATA_SCRAMBLE_EN, 1,
192 HDMI_CLOCK_CHANNEL_RATE, 1);
193 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
194
195 /* TODO: New feature for DCE11, still need to implement */
196
197 /* enable HDMI data scrambler
198 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
199 * Clock channel frequency is the same
200 * as character rate
201 */
202 REG_UPDATE_2(HDMI_CONTROL,
203 HDMI_DATA_SCRAMBLE_EN, 1,
204 HDMI_CLOCK_CHANNEL_RATE, 0);
205 }
206
207
208 /* Enable transmission of General Control packet on every frame */
209 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
210 HDMI_GC_CONT, 1,
211 HDMI_GC_SEND, 1,
212 HDMI_NULL_SEND, 1);
213
214 /* Disable Audio Content Protection packet transmission */
215 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
216
217 /* following belongs to audio */
218 /* Enable Audio InfoFrame packet transmission. */
219 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
220
221 /* update double-buffered AUDIO_INFO registers immediately */
222 ASSERT(enc->afmt);
223 enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
224
225 /* Select line number on which to send Audio InfoFrame packets */
226 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
227 VBI_LINE_0 + 2);
228
229 /* set HDMI GC AVMUTE */
230 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
231 }
232
233
234
is_two_pixels_per_containter(const struct dc_crtc_timing * timing)235 static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
236 {
237 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
238
239 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
240 && !timing->dsc_cfg.ycbcr422_simple);
241 return two_pix;
242 }
243
enc32_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)244 void enc32_stream_encoder_dp_unblank(
245 struct dc_link *link,
246 struct stream_encoder *enc,
247 const struct encoder_unblank_param *param)
248 {
249 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
250
251 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
252 uint32_t n_vid = 0x8000;
253 uint32_t m_vid;
254 uint32_t n_multiply = 0;
255 uint32_t pix_per_cycle = 0;
256 uint64_t m_vid_l = n_vid;
257
258 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
259 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1
260 || param->pix_per_cycle > 1) {
261 /*this logic should be the same in get_pixel_clock_parameters() */
262 n_multiply = 1;
263 pix_per_cycle = 1;
264 }
265 /* M / N = Fstream / Flink
266 * m_vid / n_vid = pixel rate / link rate
267 */
268
269 m_vid_l *= param->timing.pix_clk_100hz / 10;
270 m_vid_l = div_u64(m_vid_l,
271 param->link_settings.link_rate
272 * LINK_RATE_REF_FREQ_IN_KHZ);
273
274 m_vid = (uint32_t) m_vid_l;
275
276 /* enable auto measurement */
277
278 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
279
280 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
281 * therefore program initial value for Mvid and Nvid
282 */
283
284 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
285
286 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
287
288 REG_UPDATE_2(DP_VID_TIMING,
289 DP_VID_M_N_GEN_EN, 1,
290 DP_VID_N_MUL, n_multiply);
291
292 REG_UPDATE(DP_PIXEL_FORMAT,
293 DP_PIXEL_PER_CYCLE_PROCESSING_MODE,
294 pix_per_cycle);
295 }
296
297 /* make sure stream is disabled before resetting steer fifo */
298 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
299 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
300
301 /* DIG_START is removed from the register spec */
302
303 /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
304 * that it overflows during mode transition, and sometimes doesn't recover.
305 */
306 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
307 udelay(10);
308
309 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
310
311 /* DIG Resync FIFO now needs to be explicitly enabled
312 */
313 // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
314 REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
315
316 /* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1
317 * so set it to 1/2 full = 7 before reset as suggested by hardware team.
318 */
319 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
320
321 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
322
323 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
324
325 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
326
327 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
328
329 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
330
331 /* wait 100us for DIG/DP logic to prime
332 * (i.e. a few video lines)
333 */
334 udelay(100);
335
336 /* the hardware would start sending video at the start of the next DP
337 * frame (i.e. rising edge of the vblank).
338 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
339 * register has no effect on enable transition! HW always guarantees
340 * VID_STREAM enable at start of next frame, and this is not
341 * programmable
342 */
343
344 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
345
346 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
347 }
348
349 /* Set DSC-related configuration.
350 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
351 * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32
352 * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32
353 */
enc32_dp_set_dsc_config(struct stream_encoder * enc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)354 static void enc32_dp_set_dsc_config(struct stream_encoder *enc,
355 enum optc_dsc_mode dsc_mode,
356 uint32_t dsc_bytes_per_pixel,
357 uint32_t dsc_slice_width)
358 {
359 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
360
361 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);
362 }
363
364 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
365 * into a dcn_dsc_state struct.
366 */
enc32_read_state(struct stream_encoder * enc,struct enc_state * s)367 static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s)
368 {
369 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
370
371 //if dsc is enabled, continue to read
372 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
373 if (s->dsc_mode) {
374 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
375
376 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
377 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
378
379 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
380 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
381 }
382 }
383
enc32_set_dig_input_mode(struct stream_encoder * enc,unsigned int pix_per_container)384 static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
385 {
386 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
387
388 /* The naming of this field is confusing, what it means is the output mode of otg, which
389 * is the input mode of the dig
390 */
391 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);
392 }
393
enc32_reset_fifo(struct stream_encoder * enc,bool reset)394 static void enc32_reset_fifo(struct stream_encoder *enc, bool reset)
395 {
396 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
397 uint32_t reset_val = reset ? 1 : 0;
398 uint32_t is_symclk_on;
399
400 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
401 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on);
402
403 if (is_symclk_on)
404 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
405 else
406 udelay(10);
407 }
408
enc32_enable_fifo(struct stream_encoder * enc)409 void enc32_enable_fifo(struct stream_encoder *enc)
410 {
411 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
412
413 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
414
415 enc32_reset_fifo(enc, true);
416 enc32_reset_fifo(enc, false);
417
418 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
419 }
420
421 static const struct stream_encoder_funcs dcn32_str_enc_funcs = {
422 .dp_set_odm_combine =
423 enc32_dp_set_odm_combine,
424 .dp_set_stream_attribute =
425 enc2_stream_encoder_dp_set_stream_attribute,
426 .hdmi_set_stream_attribute =
427 enc32_stream_encoder_hdmi_set_stream_attribute,
428 .dvi_set_stream_attribute =
429 enc32_stream_encoder_dvi_set_stream_attribute,
430 .set_throttled_vcp_size =
431 enc1_stream_encoder_set_throttled_vcp_size,
432 .update_hdmi_info_packets =
433 enc3_stream_encoder_update_hdmi_info_packets,
434 .stop_hdmi_info_packets =
435 enc3_stream_encoder_stop_hdmi_info_packets,
436 .update_dp_info_packets_sdp_line_num =
437 enc3_stream_encoder_update_dp_info_packets_sdp_line_num,
438 .update_dp_info_packets =
439 enc3_stream_encoder_update_dp_info_packets,
440 .stop_dp_info_packets =
441 enc1_stream_encoder_stop_dp_info_packets,
442 .dp_blank =
443 enc1_stream_encoder_dp_blank,
444 .dp_unblank =
445 enc32_stream_encoder_dp_unblank,
446 .audio_mute_control = enc3_audio_mute_control,
447
448 .dp_audio_setup = enc3_se_dp_audio_setup,
449 .dp_audio_enable = enc3_se_dp_audio_enable,
450 .dp_audio_disable = enc1_se_dp_audio_disable,
451
452 .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
453 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
454 .setup_stereo_sync = enc1_setup_stereo_sync,
455 .set_avmute = enc1_stream_encoder_set_avmute,
456 .dig_connect_to_otg = enc1_dig_connect_to_otg,
457 .dig_source_otg = enc1_dig_source_otg,
458
459 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
460
461 .enc_read_state = enc32_read_state,
462 .dp_set_dsc_config = enc32_dp_set_dsc_config,
463 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
464 .set_dynamic_metadata = enc2_set_dynamic_metadata,
465 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
466
467 .set_input_mode = enc32_set_dig_input_mode,
468 .enable_fifo = enc32_enable_fifo,
469 };
470
dcn32_dio_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,struct vpg * vpg,struct afmt * afmt,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)471 void dcn32_dio_stream_encoder_construct(
472 struct dcn10_stream_encoder *enc1,
473 struct dc_context *ctx,
474 struct dc_bios *bp,
475 enum engine_id eng_id,
476 struct vpg *vpg,
477 struct afmt *afmt,
478 const struct dcn10_stream_enc_registers *regs,
479 const struct dcn10_stream_encoder_shift *se_shift,
480 const struct dcn10_stream_encoder_mask *se_mask)
481 {
482 enc1->base.funcs = &dcn32_str_enc_funcs;
483 enc1->base.ctx = ctx;
484 enc1->base.id = eng_id;
485 enc1->base.bp = bp;
486 enc1->base.vpg = vpg;
487 enc1->base.afmt = afmt;
488 enc1->regs = regs;
489 enc1->se_shift = se_shift;
490 enc1->se_mask = se_mask;
491 enc1->base.stream_enc_inst = vpg->inst;
492 }
493
494