1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "amdgpu_jpeg.h"
26 #include "amdgpu_pm.h"
27 #include "soc15.h"
28 #include "soc15d.h"
29 #include "jpeg_v2_0.h"
30 #include "jpeg_v4_0_3.h"
31
32 #include "vcn/vcn_5_0_0_offset.h"
33 #include "vcn/vcn_5_0_0_sh_mask.h"
34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
35 #include "jpeg_v5_0_0.h"
36
37 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
38 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
39 static int jpeg_v5_0_0_set_powergating_state(void *handle,
40 enum amd_powergating_state state);
41
42 /**
43 * jpeg_v5_0_0_early_init - set function pointers
44 *
45 * @handle: amdgpu_device pointer
46 *
47 * Set ring and irq function pointers
48 */
jpeg_v5_0_0_early_init(void * handle)49 static int jpeg_v5_0_0_early_init(void *handle)
50 {
51 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
52
53 adev->jpeg.num_jpeg_inst = 1;
54 adev->jpeg.num_jpeg_rings = 1;
55
56 jpeg_v5_0_0_set_dec_ring_funcs(adev);
57 jpeg_v5_0_0_set_irq_funcs(adev);
58
59 return 0;
60 }
61
62 /**
63 * jpeg_v5_0_0_sw_init - sw init for JPEG block
64 *
65 * @handle: amdgpu_device pointer
66 *
67 * Load firmware and sw initialization
68 */
jpeg_v5_0_0_sw_init(void * handle)69 static int jpeg_v5_0_0_sw_init(void *handle)
70 {
71 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
72 struct amdgpu_ring *ring;
73 int r;
74
75 /* JPEG TRAP */
76 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
77 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
78 if (r)
79 return r;
80
81 r = amdgpu_jpeg_sw_init(adev);
82 if (r)
83 return r;
84
85 r = amdgpu_jpeg_resume(adev);
86 if (r)
87 return r;
88
89 ring = adev->jpeg.inst->ring_dec;
90 ring->use_doorbell = true;
91 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
92 ring->vm_hub = AMDGPU_MMHUB0(0);
93
94 sprintf(ring->name, "jpeg_dec");
95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
96 AMDGPU_RING_PRIO_DEFAULT, NULL);
97 if (r)
98 return r;
99
100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
102
103 return 0;
104 }
105
106 /**
107 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block
108 *
109 * @handle: amdgpu_device pointer
110 *
111 * JPEG suspend and free up sw allocation
112 */
jpeg_v5_0_0_sw_fini(void * handle)113 static int jpeg_v5_0_0_sw_fini(void *handle)
114 {
115 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
116 int r;
117
118 r = amdgpu_jpeg_suspend(adev);
119 if (r)
120 return r;
121
122 r = amdgpu_jpeg_sw_fini(adev);
123
124 return r;
125 }
126
127 /**
128 * jpeg_v5_0_0_hw_init - start and test JPEG block
129 *
130 * @handle: amdgpu_device pointer
131 *
132 */
jpeg_v5_0_0_hw_init(void * handle)133 static int jpeg_v5_0_0_hw_init(void *handle)
134 {
135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
136 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
137 int r;
138
139 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
140 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
141
142 /* Skip ring test because pause DPG is not implemented. */
143 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG)
144 return 0;
145
146 r = amdgpu_ring_test_helper(ring);
147 if (r)
148 return r;
149
150 return 0;
151 }
152
153 /**
154 * jpeg_v5_0_0_hw_fini - stop the hardware block
155 *
156 * @handle: amdgpu_device pointer
157 *
158 * Stop the JPEG block, mark ring as not ready any more
159 */
jpeg_v5_0_0_hw_fini(void * handle)160 static int jpeg_v5_0_0_hw_fini(void *handle)
161 {
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
163
164 cancel_delayed_work_sync(&adev->vcn.idle_work);
165
166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
167 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
168 jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
169
170 return 0;
171 }
172
173 /**
174 * jpeg_v5_0_0_suspend - suspend JPEG block
175 *
176 * @handle: amdgpu_device pointer
177 *
178 * HW fini and suspend JPEG block
179 */
jpeg_v5_0_0_suspend(void * handle)180 static int jpeg_v5_0_0_suspend(void *handle)
181 {
182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
183 int r;
184
185 r = jpeg_v5_0_0_hw_fini(adev);
186 if (r)
187 return r;
188
189 r = amdgpu_jpeg_suspend(adev);
190
191 return r;
192 }
193
194 /**
195 * jpeg_v5_0_0_resume - resume JPEG block
196 *
197 * @handle: amdgpu_device pointer
198 *
199 * Resume firmware and hw init JPEG block
200 */
jpeg_v5_0_0_resume(void * handle)201 static int jpeg_v5_0_0_resume(void *handle)
202 {
203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
204 int r;
205
206 r = amdgpu_jpeg_resume(adev);
207 if (r)
208 return r;
209
210 r = jpeg_v5_0_0_hw_init(adev);
211
212 return r;
213 }
214
jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device * adev)215 static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev)
216 {
217 uint32_t data = 0;
218
219 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
220
221 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
222 data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK
223 | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK);
224 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
225 }
226
jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device * adev)227 static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)
228 {
229 uint32_t data = 0;
230
231 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
232
233 data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT;
234 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
235
236 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
237 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK
238 |JPEG_CGC_GATE__JPEG_ENC_MASK
239 |JPEG_CGC_GATE__JMCIF_MASK
240 |JPEG_CGC_GATE__JRBBM_MASK);
241 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
242 }
243
jpeg_v5_0_0_disable_power_gating(struct amdgpu_device * adev)244 static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)
245 {
246 uint32_t data = 0;
247
248 data = 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT;
249 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data);
250 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0,
251 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
252
253 /* disable anti hang mechanism */
254 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
255 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
256
257 return 0;
258 }
259
jpeg_v5_0_0_enable_power_gating(struct amdgpu_device * adev)260 static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)
261 {
262 /* enable anti hang mechanism */
263 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
264 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
265 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
266
267 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
268 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
269 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
270 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
271 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
272 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
273 }
274
275 return 0;
276 }
277
jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device * adev,int inst_idx,uint8_t indirect)278 static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev,
279 int inst_idx, uint8_t indirect)
280 {
281 uint32_t data = 0;
282
283 // JPEG disable CGC
284 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
285 data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
286 else
287 data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
288
289 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
290 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
291
292 if (indirect) {
293 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
294
295 // Turn on All JPEG clocks
296 data = 0;
297 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
298 } else {
299 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
300
301 // Turn on All JPEG clocks
302 data = 0;
303 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
304 }
305 }
306
307 /**
308 * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode
309 *
310 * @adev: amdgpu_device pointer
311 * @inst_idx: instance number index
312 * @indirect: indirectly write sram
313 *
314 * Start JPEG block with dpg mode
315 */
jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)316 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
317 {
318 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
319 uint32_t reg_data = 0;
320
321 jpeg_v5_0_0_enable_power_gating(adev);
322
323 // enable dynamic power gating mode
324 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
325 reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
326 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
327
328 if (indirect)
329 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
330 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
331
332 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);
333
334 /* MJPEG global tiling registers */
335 if (indirect)
336 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
337 adev->gfx.config.gb_addr_config, indirect);
338 else
339 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
340 adev->gfx.config.gb_addr_config, 1);
341
342 /* enable System Interrupt for JRBC */
343 if (indirect)
344 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN,
345 JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);
346 else
347 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN,
348 JPEG_SYS_INT_EN__DJRBC0_MASK, 1);
349
350 if (indirect) {
351 /* add nop to workaround PSP size check */
352 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);
353
354 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);
355 }
356
357 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
358 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
359 VCN_JPEG_DB_CTRL__EN_MASK);
360
361 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);
362 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
363 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
364 lower_32_bits(ring->gpu_addr));
365 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
366 upper_32_bits(ring->gpu_addr));
367 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);
368 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
369 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);
370 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
371 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
372
373 return 0;
374 }
375
376 /**
377 * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode
378 *
379 * @adev: amdgpu_device pointer
380 * @inst_idx: instance number index
381 *
382 * Stop JPEG block with dpg mode
383 */
jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device * adev,int inst_idx)384 static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
385 {
386 uint32_t reg_data = 0;
387
388 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
389 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
390 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
391 }
392
393 /**
394 * jpeg_v5_0_0_start - start JPEG block
395 *
396 * @adev: amdgpu_device pointer
397 *
398 * Setup and start the JPEG block
399 */
jpeg_v5_0_0_start(struct amdgpu_device * adev)400 static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
401 {
402 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
403 int r;
404
405 if (adev->pm.dpm_enabled)
406 amdgpu_dpm_enable_jpeg(adev, true);
407
408 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
409 r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram);
410 return r;
411 }
412
413 /* disable power gating */
414 r = jpeg_v5_0_0_disable_power_gating(adev);
415 if (r)
416 return r;
417
418 /* JPEG disable CGC */
419 jpeg_v5_0_0_disable_clock_gating(adev);
420
421 /* MJPEG global tiling registers */
422 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
423 adev->gfx.config.gb_addr_config);
424
425 /* enable JMI channel */
426 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
427 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
428
429 /* enable System Interrupt for JRBC */
430 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
431 JPEG_SYS_INT_EN__DJRBC0_MASK,
432 ~JPEG_SYS_INT_EN__DJRBC0_MASK);
433
434 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
435 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
436 VCN_JPEG_DB_CTRL__EN_MASK);
437
438 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
439 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
440 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
441 lower_32_bits(ring->gpu_addr));
442 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
443 upper_32_bits(ring->gpu_addr));
444 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
445 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
446 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
447 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
448 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
449
450 return 0;
451 }
452
453 /**
454 * jpeg_v5_0_0_stop - stop JPEG block
455 *
456 * @adev: amdgpu_device pointer
457 *
458 * stop the JPEG block
459 */
jpeg_v5_0_0_stop(struct amdgpu_device * adev)460 static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)
461 {
462 int r;
463
464 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
465 jpeg_v5_0_0_stop_dpg_mode(adev, 0);
466 } else {
467
468 /* reset JMI */
469 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
470 UVD_JMI_CNTL__SOFT_RESET_MASK,
471 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
472
473 jpeg_v5_0_0_enable_clock_gating(adev);
474
475 /* enable power gating */
476 r = jpeg_v5_0_0_enable_power_gating(adev);
477 if (r)
478 return r;
479 }
480
481 if (adev->pm.dpm_enabled)
482 amdgpu_dpm_enable_jpeg(adev, false);
483
484 return 0;
485 }
486
487 /**
488 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer
489 *
490 * @ring: amdgpu_ring pointer
491 *
492 * Returns the current hardware read pointer
493 */
jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring * ring)494 static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
495 {
496 struct amdgpu_device *adev = ring->adev;
497
498 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
499 }
500
501 /**
502 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer
503 *
504 * @ring: amdgpu_ring pointer
505 *
506 * Returns the current hardware write pointer
507 */
jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring * ring)508 static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
509 {
510 struct amdgpu_device *adev = ring->adev;
511
512 if (ring->use_doorbell)
513 return *ring->wptr_cpu_addr;
514 else
515 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
516 }
517
518 /**
519 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer
520 *
521 * @ring: amdgpu_ring pointer
522 *
523 * Commits the write pointer to the hardware
524 */
jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring * ring)525 static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
526 {
527 struct amdgpu_device *adev = ring->adev;
528
529 if (ring->use_doorbell) {
530 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
531 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
532 } else {
533 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
534 }
535 }
536
jpeg_v5_0_0_is_idle(void * handle)537 static bool jpeg_v5_0_0_is_idle(void *handle)
538 {
539 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
540 int ret = 1;
541
542 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
543 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
544 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
545
546 return ret;
547 }
548
jpeg_v5_0_0_wait_for_idle(void * handle)549 static int jpeg_v5_0_0_wait_for_idle(void *handle)
550 {
551 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
552
553 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
554 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
555 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
556 }
557
jpeg_v5_0_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)558 static int jpeg_v5_0_0_set_clockgating_state(void *handle,
559 enum amd_clockgating_state state)
560 {
561 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
562 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
563
564 if (enable) {
565 if (!jpeg_v5_0_0_is_idle(handle))
566 return -EBUSY;
567 jpeg_v5_0_0_enable_clock_gating(adev);
568 } else {
569 jpeg_v5_0_0_disable_clock_gating(adev);
570 }
571
572 return 0;
573 }
574
jpeg_v5_0_0_set_powergating_state(void * handle,enum amd_powergating_state state)575 static int jpeg_v5_0_0_set_powergating_state(void *handle,
576 enum amd_powergating_state state)
577 {
578 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
579 int ret;
580
581 if (state == adev->jpeg.cur_state)
582 return 0;
583
584 if (state == AMD_PG_STATE_GATE)
585 ret = jpeg_v5_0_0_stop(adev);
586 else
587 ret = jpeg_v5_0_0_start(adev);
588
589 if (!ret)
590 adev->jpeg.cur_state = state;
591
592 return ret;
593 }
594
jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)595 static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev,
596 struct amdgpu_irq_src *source,
597 unsigned int type,
598 enum amdgpu_interrupt_state state)
599 {
600 return 0;
601 }
602
jpeg_v5_0_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)603 static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,
604 struct amdgpu_irq_src *source,
605 struct amdgpu_iv_entry *entry)
606 {
607 DRM_DEBUG("IH: JPEG TRAP\n");
608
609 switch (entry->src_id) {
610 case VCN_4_0__SRCID__JPEG_DECODE:
611 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
612 break;
613 default:
614 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
615 entry->src_id, entry->src_data[0]);
616 break;
617 }
618
619 return 0;
620 }
621
622 static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
623 .name = "jpeg_v5_0_0",
624 .early_init = jpeg_v5_0_0_early_init,
625 .late_init = NULL,
626 .sw_init = jpeg_v5_0_0_sw_init,
627 .sw_fini = jpeg_v5_0_0_sw_fini,
628 .hw_init = jpeg_v5_0_0_hw_init,
629 .hw_fini = jpeg_v5_0_0_hw_fini,
630 .suspend = jpeg_v5_0_0_suspend,
631 .resume = jpeg_v5_0_0_resume,
632 .is_idle = jpeg_v5_0_0_is_idle,
633 .wait_for_idle = jpeg_v5_0_0_wait_for_idle,
634 .check_soft_reset = NULL,
635 .pre_soft_reset = NULL,
636 .soft_reset = NULL,
637 .post_soft_reset = NULL,
638 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
639 .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
640 .dump_ip_state = NULL,
641 .print_ip_state = NULL,
642 };
643
644 static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
645 .type = AMDGPU_RING_TYPE_VCN_JPEG,
646 .align_mask = 0xf,
647 .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
648 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
649 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
650 .parse_cs = jpeg_v2_dec_ring_parse_cs,
651 .emit_frame_size =
652 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
653 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
654 8 + /* jpeg_v5_0_0_dec_ring_emit_vm_flush */
655 22 + 22 + /* jpeg_v5_0_0_dec_ring_emit_fence x2 vm fence */
656 8 + 16,
657 .emit_ib_size = 22, /* jpeg_v5_0_0_dec_ring_emit_ib */
658 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
659 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
660 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
661 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
662 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
663 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
664 .insert_start = jpeg_v4_0_3_dec_ring_insert_start,
665 .insert_end = jpeg_v4_0_3_dec_ring_insert_end,
666 .pad_ib = amdgpu_ring_generic_pad_ib,
667 .begin_use = amdgpu_jpeg_ring_begin_use,
668 .end_use = amdgpu_jpeg_ring_end_use,
669 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
670 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
671 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
672 };
673
jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device * adev)674 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
675 {
676 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
677 }
678
679 static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
680 .set = jpeg_v5_0_0_set_interrupt_state,
681 .process = jpeg_v5_0_0_process_interrupt,
682 };
683
jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device * adev)684 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
685 {
686 adev->jpeg.inst->irq.num_types = 1;
687 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;
688 }
689
690 const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = {
691 .type = AMD_IP_BLOCK_TYPE_JPEG,
692 .major = 5,
693 .minor = 0,
694 .rev = 0,
695 .funcs = &jpeg_v5_0_0_ip_funcs,
696 };
697