1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Cavium, Inc.
7 *
8 * Copyright (C) 2009 Wind River Systems,
9 * written by Ralf Baechle <ralf@linux-mips.org>
10 */
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/edac.h>
17
18 #include "edac_module.h"
19
20 #include <asm/octeon/cvmx.h>
21 #include <asm/mipsregs.h>
22
23 extern int register_co_cache_error_notifier(struct notifier_block *nb);
24 extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
25
26 extern unsigned long long cache_err_dcache[NR_CPUS];
27
28 struct co_cache_error {
29 struct notifier_block notifier;
30 struct edac_device_ctl_info *ed;
31 };
32
33 /**
34 * EDAC CPU cache error callback
35 *
36 * @event: non-zero if unrecoverable.
37 */
co_cache_error_event(struct notifier_block * this,unsigned long event,void * ptr)38 static int co_cache_error_event(struct notifier_block *this,
39 unsigned long event, void *ptr)
40 {
41 struct co_cache_error *p = container_of(this, struct co_cache_error,
42 notifier);
43
44 unsigned int core = cvmx_get_core_num();
45 unsigned int cpu = smp_processor_id();
46 u64 icache_err = read_octeon_c0_icacheerr();
47 u64 dcache_err;
48
49 if (event) {
50 dcache_err = cache_err_dcache[core];
51 cache_err_dcache[core] = 0;
52 } else {
53 dcache_err = read_octeon_c0_dcacheerr();
54 }
55
56 if (icache_err & 1) {
57 edac_device_printk(p->ed, KERN_ERR,
58 "CacheErr (Icache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
59 (unsigned long long)icache_err, core, cpu,
60 read_c0_errorepc());
61 write_octeon_c0_icacheerr(0);
62 edac_device_handle_ce(p->ed, cpu, 1, "icache");
63 }
64 if (dcache_err & 1) {
65 edac_device_printk(p->ed, KERN_ERR,
66 "CacheErr (Dcache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
67 (unsigned long long)dcache_err, core, cpu,
68 read_c0_errorepc());
69 if (event)
70 edac_device_handle_ue(p->ed, cpu, 0, "dcache");
71 else
72 edac_device_handle_ce(p->ed, cpu, 0, "dcache");
73
74 /* Clear the error indication */
75 if (OCTEON_IS_OCTEON2())
76 write_octeon_c0_dcacheerr(1);
77 else
78 write_octeon_c0_dcacheerr(0);
79 }
80
81 return NOTIFY_STOP;
82 }
83
co_cache_error_probe(struct platform_device * pdev)84 static int co_cache_error_probe(struct platform_device *pdev)
85 {
86 struct co_cache_error *p = devm_kzalloc(&pdev->dev, sizeof(*p),
87 GFP_KERNEL);
88 if (!p)
89 return -ENOMEM;
90
91 p->notifier.notifier_call = co_cache_error_event;
92 platform_set_drvdata(pdev, p);
93
94 p->ed = edac_device_alloc_ctl_info(0, "cpu", num_possible_cpus(),
95 "cache", 2, 0,
96 edac_device_alloc_index());
97 if (!p->ed)
98 goto err;
99
100 p->ed->dev = &pdev->dev;
101
102 p->ed->dev_name = dev_name(&pdev->dev);
103
104 p->ed->mod_name = "octeon-cpu";
105 p->ed->ctl_name = "cache";
106
107 if (edac_device_add_device(p->ed)) {
108 pr_err("%s: edac_device_add_device() failed\n", __func__);
109 goto err1;
110 }
111
112 register_co_cache_error_notifier(&p->notifier);
113
114 return 0;
115
116 err1:
117 edac_device_free_ctl_info(p->ed);
118 err:
119 return -ENXIO;
120 }
121
co_cache_error_remove(struct platform_device * pdev)122 static void co_cache_error_remove(struct platform_device *pdev)
123 {
124 struct co_cache_error *p = platform_get_drvdata(pdev);
125
126 unregister_co_cache_error_notifier(&p->notifier);
127 edac_device_del_device(&pdev->dev);
128 edac_device_free_ctl_info(p->ed);
129 }
130
131 static struct platform_driver co_cache_error_driver = {
132 .probe = co_cache_error_probe,
133 .remove_new = co_cache_error_remove,
134 .driver = {
135 .name = "octeon_pc_edac",
136 }
137 };
138 module_platform_driver(co_cache_error_driver);
139
140 MODULE_DESCRIPTION("Cavium Octeon Primary Caches EDAC driver");
141 MODULE_LICENSE("GPL");
142 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
143