1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r8a7740 Core CPG Clocks
4 *
5 * Copyright (C) 2014 Ulrich Hecht
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/spinlock.h>
17
18 struct r8a7740_cpg {
19 struct clk_onecell_data data;
20 spinlock_t lock;
21 };
22
23 #define CPG_FRQCRA 0x00
24 #define CPG_FRQCRB 0x04
25 #define CPG_PLLC2CR 0x2c
26 #define CPG_USBCKCR 0x8c
27 #define CPG_FRQCRC 0xe0
28
29 struct div4_clk {
30 const char *name;
31 unsigned int reg;
32 unsigned int shift;
33 };
34
35 static struct div4_clk div4_clks[] = {
36 { "i", CPG_FRQCRA, 20 },
37 { "zg", CPG_FRQCRA, 16 },
38 { "b", CPG_FRQCRA, 8 },
39 { "m1", CPG_FRQCRA, 4 },
40 { "hp", CPG_FRQCRB, 4 },
41 { "hpp", CPG_FRQCRC, 20 },
42 { "usbp", CPG_FRQCRC, 16 },
43 { "s", CPG_FRQCRC, 12 },
44 { "zb", CPG_FRQCRC, 8 },
45 { "m3", CPG_FRQCRC, 4 },
46 { "cp", CPG_FRQCRC, 0 },
47 { NULL, 0, 0 },
48 };
49
50 static const struct clk_div_table div4_div_table[] = {
51 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
52 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
53 { 13, 72 }, { 14, 96 }, { 0, 0 }
54 };
55
56 static u32 cpg_mode __initdata;
57
58 static struct clk * __init
r8a7740_cpg_register_clock(struct device_node * np,struct r8a7740_cpg * cpg,void __iomem * base,const char * name)59 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
60 void __iomem *base, const char *name)
61 {
62 const struct clk_div_table *table = NULL;
63 const char *parent_name;
64 unsigned int shift, reg;
65 unsigned int mult = 1;
66 unsigned int div = 1;
67
68 if (!strcmp(name, "r")) {
69 switch (cpg_mode & (BIT(2) | BIT(1))) {
70 case BIT(1) | BIT(2):
71 /* extal1 */
72 parent_name = of_clk_get_parent_name(np, 0);
73 div = 2048;
74 break;
75 case BIT(2):
76 /* extal1 */
77 parent_name = of_clk_get_parent_name(np, 0);
78 div = 1024;
79 break;
80 default:
81 /* extalr */
82 parent_name = of_clk_get_parent_name(np, 2);
83 break;
84 }
85 } else if (!strcmp(name, "system")) {
86 parent_name = of_clk_get_parent_name(np, 0);
87 if (cpg_mode & BIT(1))
88 div = 2;
89 } else if (!strcmp(name, "pllc0")) {
90 /* PLLC0/1 are configurable multiplier clocks. Register them as
91 * fixed factor clocks for now as there's no generic multiplier
92 * clock implementation and we currently have no need to change
93 * the multiplier value.
94 */
95 u32 value = readl(base + CPG_FRQCRC);
96 parent_name = "system";
97 mult = ((value >> 24) & 0x7f) + 1;
98 } else if (!strcmp(name, "pllc1")) {
99 u32 value = readl(base + CPG_FRQCRA);
100 parent_name = "system";
101 mult = ((value >> 24) & 0x7f) + 1;
102 div = 2;
103 } else if (!strcmp(name, "pllc2")) {
104 u32 value = readl(base + CPG_PLLC2CR);
105 parent_name = "system";
106 mult = ((value >> 24) & 0x3f) + 1;
107 } else if (!strcmp(name, "usb24s")) {
108 u32 value = readl(base + CPG_USBCKCR);
109 if (value & BIT(7))
110 /* extal2 */
111 parent_name = of_clk_get_parent_name(np, 1);
112 else
113 parent_name = "system";
114 if (!(value & BIT(6)))
115 div = 2;
116 } else {
117 struct div4_clk *c;
118 for (c = div4_clks; c->name; c++) {
119 if (!strcmp(name, c->name)) {
120 parent_name = "pllc1";
121 table = div4_div_table;
122 reg = c->reg;
123 shift = c->shift;
124 break;
125 }
126 }
127 if (!c->name)
128 return ERR_PTR(-EINVAL);
129 }
130
131 if (!table) {
132 return clk_register_fixed_factor(NULL, name, parent_name, 0,
133 mult, div);
134 } else {
135 return clk_register_divider_table(NULL, name, parent_name, 0,
136 base + reg, shift, 4, 0,
137 table, &cpg->lock);
138 }
139 }
140
r8a7740_cpg_clocks_init(struct device_node * np)141 static void __init r8a7740_cpg_clocks_init(struct device_node *np)
142 {
143 struct r8a7740_cpg *cpg;
144 void __iomem *base;
145 struct clk **clks;
146 unsigned int i;
147 int num_clks;
148
149 if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
150 pr_warn("%s: missing renesas,mode property\n", __func__);
151
152 num_clks = of_property_count_strings(np, "clock-output-names");
153 if (num_clks < 0) {
154 pr_err("%s: failed to count clocks\n", __func__);
155 return;
156 }
157
158 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
159 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
160 if (cpg == NULL || clks == NULL) {
161 /* We're leaking memory on purpose, there's no point in cleaning
162 * up as the system won't boot anyway.
163 */
164 return;
165 }
166
167 spin_lock_init(&cpg->lock);
168
169 cpg->data.clks = clks;
170 cpg->data.clk_num = num_clks;
171
172 base = of_iomap(np, 0);
173 if (WARN_ON(base == NULL))
174 return;
175
176 for (i = 0; i < num_clks; ++i) {
177 const char *name;
178 struct clk *clk;
179
180 of_property_read_string_index(np, "clock-output-names", i,
181 &name);
182
183 clk = r8a7740_cpg_register_clock(np, cpg, base, name);
184 if (IS_ERR(clk))
185 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
186 __func__, np, name, PTR_ERR(clk));
187 else
188 cpg->data.clks[i] = clk;
189 }
190
191 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
192 }
193 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
194 r8a7740_cpg_clocks_init);
195