1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6 #include <linux/firmware.h>
7 #include <linux/highmem.h>
8 #include <linux/moduleparam.h>
9 #include <linux/pci.h>
10
11 #include "vpu_boot_api.h"
12 #include "ivpu_drv.h"
13 #include "ivpu_fw.h"
14 #include "ivpu_fw_log.h"
15 #include "ivpu_gem.h"
16 #include "ivpu_hw.h"
17 #include "ivpu_ipc.h"
18 #include "ivpu_pm.h"
19
20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G)
21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G)
22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */
23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */
24 #define FW_RUNTIME_MAX_SIZE SZ_512M
25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M
26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START)
27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE)
28 #define FW_VERSION_HEADER_SIZE SZ_4K
29 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
30
31 #define WATCHDOG_MSS_REDIRECT 32
32 #define WATCHDOG_NCE_REDIRECT 33
33
34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31)
35
36 /* Check if FW API is compatible with the driver */
37 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \
38 ivpu_fw_check_api(vdev, fw_hdr, #name, \
39 VPU_##name##_API_VER_INDEX, \
40 VPU_##name##_API_VER_MAJOR, \
41 VPU_##name##_API_VER_MINOR, min_major)
42
43 /* Check if API version is lower that the given version */
44 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
45 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
46
47 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000
48
49 static char *ivpu_firmware;
50 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
51 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
52
53 static struct {
54 int gen;
55 const char *name;
56 } fw_names[] = {
57 { IVPU_HW_IP_37XX, "vpu_37xx.bin" },
58 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
59 { IVPU_HW_IP_40XX, "vpu_40xx.bin" },
60 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
61 };
62
63 /* Production fw_names from the table above */
64 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin");
65 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin");
66
ivpu_fw_request(struct ivpu_device * vdev)67 static int ivpu_fw_request(struct ivpu_device *vdev)
68 {
69 int ret = -ENOENT;
70 int i;
71
72 if (ivpu_firmware) {
73 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev);
74 if (!ret)
75 vdev->fw->name = ivpu_firmware;
76 return ret;
77 }
78
79 for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
80 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev))
81 continue;
82
83 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
84 if (!ret) {
85 vdev->fw->name = fw_names[i].name;
86 return 0;
87 }
88 }
89
90 ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
91 return ret;
92 }
93
94 static int
ivpu_fw_check_api(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr,const char * str,int index,u16 expected_major,u16 expected_minor,u16 min_major)95 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
96 const char *str, int index, u16 expected_major, u16 expected_minor,
97 u16 min_major)
98 {
99 u16 major = (u16)(fw_hdr->api_version[index] >> 16);
100 u16 minor = (u16)(fw_hdr->api_version[index]);
101
102 if (major < min_major) {
103 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
104 str, major, minor, min_major);
105 return -EINVAL;
106 }
107 if (major != expected_major) {
108 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n",
109 str, major, minor, expected_major, expected_minor);
110 }
111 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
112 str, major, minor, expected_major, expected_minor);
113
114 return 0;
115 }
116
117 static bool
ivpu_fw_check_api_ver_lt(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr,const char * str,int index,u16 major,u16 minor)118 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
119 const char *str, int index, u16 major, u16 minor)
120 {
121 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16);
122 u16 fw_minor = (u16)(fw_hdr->api_version[index]);
123
124 if (fw_major < major || (fw_major == major && fw_minor < minor))
125 return true;
126
127 return false;
128 }
129
is_within_range(u64 addr,size_t size,u64 range_start,size_t range_size)130 static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size)
131 {
132 if (addr < range_start || addr + size > range_start + range_size)
133 return false;
134
135 return true;
136 }
137
ivpu_fw_parse(struct ivpu_device * vdev)138 static int ivpu_fw_parse(struct ivpu_device *vdev)
139 {
140 struct ivpu_fw_info *fw = vdev->fw;
141 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data;
142 u64 runtime_addr, image_load_addr, runtime_size, image_size;
143
144 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) {
145 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
146 return -EINVAL;
147 }
148
149 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) {
150 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
151 return -EINVAL;
152 }
153
154 runtime_addr = fw_hdr->boot_params_load_address;
155 runtime_size = fw_hdr->runtime_size;
156 image_load_addr = fw_hdr->image_load_address;
157 image_size = fw_hdr->image_size;
158
159 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) {
160 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr);
161 return -EINVAL;
162 }
163
164 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) {
165 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size);
166 return -EINVAL;
167 }
168
169 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) {
170 ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
171 return -EINVAL;
172 }
173
174 if (image_load_addr < runtime_addr ||
175 image_load_addr + image_size > runtime_addr + runtime_size) {
176 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n",
177 image_load_addr, image_size);
178 return -EINVAL;
179 }
180
181 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) {
182 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
183 return -EINVAL;
184 }
185
186 if (fw_hdr->entry_point < image_load_addr ||
187 fw_hdr->entry_point >= image_load_addr + image_size) {
188 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
189 return -EINVAL;
190 }
191 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
192 fw_hdr->header_version, fw_hdr->image_format);
193
194 ivpu_info(vdev, "Firmware: %s, version: %s", fw->name,
195 (const char *)fw_hdr + VPU_FW_HEADER_SIZE);
196
197 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
198 return -EINVAL;
199 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3))
200 return -EINVAL;
201
202 fw->runtime_addr = runtime_addr;
203 fw->runtime_size = runtime_size;
204 fw->image_load_offset = image_load_addr - runtime_addr;
205 fw->image_size = image_size;
206 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size);
207
208 fw->cold_boot_entry_point = fw_hdr->entry_point;
209 fw->entry_point = fw->cold_boot_entry_point;
210
211 fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL);
212 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
213 fw->trace_hw_component_mask = -1;
214
215 fw->dvfs_mode = 0;
216
217 fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
218 fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
219
220 if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address,
221 fw_hdr->ro_section_size,
222 fw_hdr->image_load_address,
223 fw_hdr->image_size)) {
224 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
225 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size);
226 return -EINVAL;
227 }
228
229 fw->read_only_addr = fw_hdr->ro_section_start_address;
230 fw->read_only_size = fw_hdr->ro_section_size;
231
232 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n",
233 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size);
234 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n",
235 fw->runtime_addr, image_load_addr, fw->entry_point);
236 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
237 fw->read_only_addr, fw->read_only_size);
238
239 return 0;
240 }
241
ivpu_fw_release(struct ivpu_device * vdev)242 static void ivpu_fw_release(struct ivpu_device *vdev)
243 {
244 release_firmware(vdev->fw->file);
245 }
246
247 /* Initialize workarounds that depend on FW version */
248 static void
ivpu_fw_init_wa(struct ivpu_device * vdev)249 ivpu_fw_init_wa(struct ivpu_device *vdev)
250 {
251 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
252
253 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
254 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
255 vdev->wa.disable_d0i3_msg = true;
256
257 /* Force enable the feature for testing purposes */
258 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
259 vdev->wa.disable_d0i3_msg = false;
260
261 IVPU_PRINT_WA(disable_d0i3_msg);
262 }
263
ivpu_fw_update_global_range(struct ivpu_device * vdev)264 static int ivpu_fw_update_global_range(struct ivpu_device *vdev)
265 {
266 struct ivpu_fw_info *fw = vdev->fw;
267 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT);
268 u64 size = FW_SHARED_MEM_SIZE;
269
270 if (start + size > FW_GLOBAL_MEM_END) {
271 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size);
272 return -EINVAL;
273 }
274
275 ivpu_hw_range_init(&vdev->hw->ranges.global, start, size);
276 return 0;
277 }
278
ivpu_fw_mem_init(struct ivpu_device * vdev)279 static int ivpu_fw_mem_init(struct ivpu_device *vdev)
280 {
281 struct ivpu_fw_info *fw = vdev->fw;
282 struct ivpu_addr_range fw_range;
283 int log_verb_size;
284 int ret;
285
286 ret = ivpu_fw_update_global_range(vdev);
287 if (ret)
288 return ret;
289
290 fw_range.start = fw->runtime_addr;
291 fw_range.end = fw->runtime_addr + fw->runtime_size;
292 fw->mem = ivpu_bo_create(vdev, &vdev->gctx, &fw_range, fw->runtime_size,
293 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
294 if (!fw->mem) {
295 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n");
296 return -ENOMEM;
297 }
298
299 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr,
300 fw->read_only_size);
301 if (ret) {
302 ivpu_err(vdev, "Failed to set firmware image read-only\n");
303 goto err_free_fw_mem;
304 }
305
306 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,
307 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
308 if (!fw->mem_log_crit) {
309 ivpu_err(vdev, "Failed to create critical log buffer\n");
310 ret = -ENOMEM;
311 goto err_free_fw_mem;
312 }
313
314 if (ivpu_log_level <= IVPU_FW_LOG_INFO)
315 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
316 else
317 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
318
319 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size,
320 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
321 if (!fw->mem_log_verb) {
322 ivpu_err(vdev, "Failed to create verbose log buffer\n");
323 ret = -ENOMEM;
324 goto err_free_log_crit;
325 }
326
327 if (fw->shave_nn_size) {
328 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave,
329 fw->shave_nn_size, DRM_IVPU_BO_WC);
330 if (!fw->mem_shave_nn) {
331 ivpu_err(vdev, "Failed to create shavenn buffer\n");
332 ret = -ENOMEM;
333 goto err_free_log_verb;
334 }
335 }
336
337 return 0;
338
339 err_free_log_verb:
340 ivpu_bo_free(fw->mem_log_verb);
341 err_free_log_crit:
342 ivpu_bo_free(fw->mem_log_crit);
343 err_free_fw_mem:
344 ivpu_bo_free(fw->mem);
345 return ret;
346 }
347
ivpu_fw_mem_fini(struct ivpu_device * vdev)348 static void ivpu_fw_mem_fini(struct ivpu_device *vdev)
349 {
350 struct ivpu_fw_info *fw = vdev->fw;
351
352 if (fw->mem_shave_nn) {
353 ivpu_bo_free(fw->mem_shave_nn);
354 fw->mem_shave_nn = NULL;
355 }
356
357 ivpu_bo_free(fw->mem_log_verb);
358 ivpu_bo_free(fw->mem_log_crit);
359 ivpu_bo_free(fw->mem);
360
361 fw->mem_log_verb = NULL;
362 fw->mem_log_crit = NULL;
363 fw->mem = NULL;
364 }
365
ivpu_fw_init(struct ivpu_device * vdev)366 int ivpu_fw_init(struct ivpu_device *vdev)
367 {
368 int ret;
369
370 ret = ivpu_fw_request(vdev);
371 if (ret)
372 return ret;
373
374 ret = ivpu_fw_parse(vdev);
375 if (ret)
376 goto err_fw_release;
377
378 ivpu_fw_init_wa(vdev);
379
380 ret = ivpu_fw_mem_init(vdev);
381 if (ret)
382 goto err_fw_release;
383
384 ivpu_fw_load(vdev);
385
386 return 0;
387
388 err_fw_release:
389 ivpu_fw_release(vdev);
390 return ret;
391 }
392
ivpu_fw_fini(struct ivpu_device * vdev)393 void ivpu_fw_fini(struct ivpu_device *vdev)
394 {
395 ivpu_fw_mem_fini(vdev);
396 ivpu_fw_release(vdev);
397 }
398
ivpu_fw_load(struct ivpu_device * vdev)399 void ivpu_fw_load(struct ivpu_device *vdev)
400 {
401 struct ivpu_fw_info *fw = vdev->fw;
402 u64 image_end_offset = fw->image_load_offset + fw->image_size;
403
404 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset);
405 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset,
406 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size);
407
408 if (IVPU_WA(clear_runtime_mem)) {
409 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset;
410 u64 size = ivpu_bo_size(fw->mem) - image_end_offset;
411
412 memset(start, 0, size);
413 }
414
415 wmb(); /* Flush WC buffers after writing fw->mem */
416 }
417
ivpu_fw_boot_params_print(struct ivpu_device * vdev,struct vpu_boot_params * boot_params)418 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
419 {
420 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
421 boot_params->magic);
422 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
423 boot_params->vpu_id);
424 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
425 boot_params->vpu_count);
426 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
427 boot_params->frequency);
428 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
429 boot_params->perf_clk_frequency);
430
431 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
432 boot_params->ipc_header_area_start);
433 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
434 boot_params->ipc_header_area_size);
435 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
436 boot_params->shared_region_base);
437 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
438 boot_params->shared_region_size);
439 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
440 boot_params->ipc_payload_area_start);
441 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
442 boot_params->ipc_payload_area_size);
443 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
444 boot_params->global_aliased_pio_base);
445 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
446 boot_params->global_aliased_pio_size);
447
448 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
449 boot_params->autoconfig);
450
451 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
452 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use);
453 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
454 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg);
455
456 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n",
457 boot_params->global_memory_allocator_base);
458 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n",
459 boot_params->global_memory_allocator_size);
460
461 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
462 boot_params->shave_nn_fw_base);
463
464 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
465 boot_params->watchdog_irq_mss);
466 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
467 boot_params->watchdog_irq_nce);
468 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n",
469 boot_params->host_to_vpu_irq);
470 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n",
471 boot_params->job_done_irq);
472
473 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
474 boot_params->host_version_id);
475 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
476 boot_params->si_stepping);
477 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
478 boot_params->device_id);
479 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
480 boot_params->feature_exclusion);
481 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
482 boot_params->sku);
483 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
484 boot_params->min_freq_pll_ratio);
485 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
486 boot_params->pn_freq_pll_ratio);
487 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
488 boot_params->max_freq_pll_ratio);
489 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
490 boot_params->default_trace_level);
491 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
492 boot_params->tracing_buff_message_format_mask);
493 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
494 boot_params->trace_destination_mask);
495 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
496 boot_params->trace_hw_component_mask);
497 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
498 boot_params->boot_type);
499 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
500 boot_params->punit_telemetry_sram_base);
501 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
502 boot_params->punit_telemetry_sram_size);
503 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
504 boot_params->vpu_telemetry_enable);
505 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
506 boot_params->vpu_scheduling_mode);
507 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
508 boot_params->dvfs_mode);
509 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
510 boot_params->d0i3_delayed_entry);
511 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
512 boot_params->d0i3_residency_time_us);
513 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
514 boot_params->d0i3_entry_vpu_ts);
515 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
516 boot_params->system_time_us);
517 }
518
ivpu_fw_boot_params_setup(struct ivpu_device * vdev,struct vpu_boot_params * boot_params)519 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
520 {
521 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx;
522
523 /* In case of warm boot only update variable params */
524 if (!ivpu_fw_is_cold_boot(vdev)) {
525 boot_params->d0i3_residency_time_us =
526 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts);
527 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts;
528 boot_params->system_time_us = ktime_to_us(ktime_get_real());
529
530 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
531 boot_params->d0i3_residency_time_us);
532 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
533 boot_params->d0i3_entry_vpu_ts);
534 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
535 boot_params->system_time_us);
536
537 boot_params->save_restore_ret_address = 0;
538 vdev->pm->is_warmboot = true;
539 wmb(); /* Flush WC buffers after writing save_restore_ret_address */
540 return;
541 }
542
543 vdev->pm->is_warmboot = false;
544
545 boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
546 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
547 boot_params->frequency = ivpu_hw_pll_freq_get(vdev);
548
549 /*
550 * This param is a debug firmware feature. It switches default clock
551 * to higher resolution one for fine-grained and more accurate firmware
552 * task profiling.
553 */
554 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev);
555
556 /*
557 * Uncached region of VPU address space, covers IPC buffers, job queues
558 * and log buffers, programmable to L2$ Uncached by VPU MTRR
559 */
560 boot_params->shared_region_base = vdev->hw->ranges.global.start;
561 boot_params->shared_region_size = vdev->hw->ranges.global.end -
562 vdev->hw->ranges.global.start;
563
564 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
565 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
566
567 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
568 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
569
570 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
571 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
572
573 /* Allow configuration for L2C_PAGE_TABLE with boot param value */
574 boot_params->autoconfig = 1;
575
576 /* Enable L2 cache for first 2GB of high memory */
577 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
578 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
579 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
580
581 if (vdev->fw->mem_shave_nn)
582 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
583
584 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT;
585 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT;
586 boot_params->si_stepping = ivpu_revision(vdev);
587 boot_params->device_id = ivpu_device_id(vdev);
588 boot_params->feature_exclusion = vdev->hw->tile_fuse;
589 boot_params->sku = vdev->hw->sku;
590
591 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
592 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
593 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
594
595 boot_params->default_trace_level = vdev->fw->trace_level;
596 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING);
597 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask;
598 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
599 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr;
600 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit);
601 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
602 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
603
604 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
605 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
606 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
607 boot_params->vpu_scheduling_mode = vdev->hw->sched_mode;
608 if (vdev->hw->sched_mode == VPU_SCHEDULING_MODE_HW)
609 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
610 boot_params->dvfs_mode = vdev->fw->dvfs_mode;
611 if (!IVPU_WA(disable_d0i3_msg))
612 boot_params->d0i3_delayed_entry = 1;
613 boot_params->d0i3_residency_time_us = 0;
614 boot_params->d0i3_entry_vpu_ts = 0;
615
616 boot_params->system_time_us = ktime_to_us(ktime_get_real());
617 wmb(); /* Flush WC buffers after writing bootparams */
618
619 ivpu_fw_boot_params_print(vdev, boot_params);
620 }
621