1  // SPDX-License-Identifier: GPL-2.0-or-later
2  /*
3   * PowerNV Platform dependent EEH operations
4   *
5   * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
6   */
7  
8  #include <linux/atomic.h>
9  #include <linux/debugfs.h>
10  #include <linux/delay.h>
11  #include <linux/export.h>
12  #include <linux/init.h>
13  #include <linux/interrupt.h>
14  #include <linux/irqdomain.h>
15  #include <linux/list.h>
16  #include <linux/msi.h>
17  #include <linux/of.h>
18  #include <linux/pci.h>
19  #include <linux/proc_fs.h>
20  #include <linux/rbtree.h>
21  #include <linux/sched.h>
22  #include <linux/seq_file.h>
23  #include <linux/spinlock.h>
24  
25  #include <asm/eeh.h>
26  #include <asm/eeh_event.h>
27  #include <asm/firmware.h>
28  #include <asm/io.h>
29  #include <asm/iommu.h>
30  #include <asm/machdep.h>
31  #include <asm/msi_bitmap.h>
32  #include <asm/opal.h>
33  #include <asm/ppc-pci.h>
34  #include <asm/pnv-pci.h>
35  
36  #include "powernv.h"
37  #include "pci.h"
38  #include "../../../../drivers/pci/pci.h"
39  
40  static int eeh_event_irq = -EINVAL;
41  
pnv_pcibios_bus_add_device(struct pci_dev * pdev)42  static void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
43  {
44  	dev_dbg(&pdev->dev, "EEH: Setting up device\n");
45  	eeh_probe_device(pdev);
46  }
47  
pnv_eeh_event(int irq,void * data)48  static irqreturn_t pnv_eeh_event(int irq, void *data)
49  {
50  	/*
51  	 * We simply send a special EEH event if EEH has been
52  	 * enabled. We don't care about EEH events until we've
53  	 * finished processing the outstanding ones. Event processing
54  	 * gets unmasked in next_error() if EEH is enabled.
55  	 */
56  	disable_irq_nosync(irq);
57  
58  	if (eeh_enabled())
59  		eeh_send_failure_event(NULL);
60  
61  	return IRQ_HANDLED;
62  }
63  
64  #ifdef CONFIG_DEBUG_FS
pnv_eeh_ei_write(struct file * filp,const char __user * user_buf,size_t count,loff_t * ppos)65  static ssize_t pnv_eeh_ei_write(struct file *filp,
66  				const char __user *user_buf,
67  				size_t count, loff_t *ppos)
68  {
69  	struct pci_controller *hose = filp->private_data;
70  	struct eeh_pe *pe;
71  	int pe_no, type, func;
72  	unsigned long addr, mask;
73  	char buf[50];
74  	int ret;
75  
76  	if (!eeh_ops || !eeh_ops->err_inject)
77  		return -ENXIO;
78  
79  	/* Copy over argument buffer */
80  	ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
81  	if (!ret)
82  		return -EFAULT;
83  
84  	/* Retrieve parameters */
85  	ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
86  		     &pe_no, &type, &func, &addr, &mask);
87  	if (ret != 5)
88  		return -EINVAL;
89  
90  	/* Retrieve PE */
91  	pe = eeh_pe_get(hose, pe_no);
92  	if (!pe)
93  		return -ENODEV;
94  
95  	/* Do error injection */
96  	ret = eeh_ops->err_inject(pe, type, func, addr, mask);
97  	return ret < 0 ? ret : count;
98  }
99  
100  static const struct file_operations pnv_eeh_ei_fops = {
101  	.open	= simple_open,
102  	.write	= pnv_eeh_ei_write,
103  };
104  
pnv_eeh_dbgfs_set(void * data,int offset,u64 val)105  static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
106  {
107  	struct pci_controller *hose = data;
108  	struct pnv_phb *phb = hose->private_data;
109  
110  	out_be64(phb->regs + offset, val);
111  	return 0;
112  }
113  
pnv_eeh_dbgfs_get(void * data,int offset,u64 * val)114  static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
115  {
116  	struct pci_controller *hose = data;
117  	struct pnv_phb *phb = hose->private_data;
118  
119  	*val = in_be64(phb->regs + offset);
120  	return 0;
121  }
122  
123  #define PNV_EEH_DBGFS_ENTRY(name, reg)				\
124  static int pnv_eeh_dbgfs_set_##name(void *data, u64 val)	\
125  {								\
126  	return pnv_eeh_dbgfs_set(data, reg, val);		\
127  }								\
128  								\
129  static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val)	\
130  {								\
131  	return pnv_eeh_dbgfs_get(data, reg, val);		\
132  }								\
133  								\
134  DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name,		\
135  			pnv_eeh_dbgfs_get_##name,		\
136                          pnv_eeh_dbgfs_set_##name,		\
137  			"0x%llx\n")
138  
139  PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
140  PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
141  PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
142  
143  #endif /* CONFIG_DEBUG_FS */
144  
pnv_eeh_enable_phbs(void)145  static void pnv_eeh_enable_phbs(void)
146  {
147  	struct pci_controller *hose;
148  	struct pnv_phb *phb;
149  
150  	list_for_each_entry(hose, &hose_list, list_node) {
151  		phb = hose->private_data;
152  		/*
153  		 * If EEH is enabled, we're going to rely on that.
154  		 * Otherwise, we restore to conventional mechanism
155  		 * to clear frozen PE during PCI config access.
156  		 */
157  		if (eeh_enabled())
158  			phb->flags |= PNV_PHB_FLAG_EEH;
159  		else
160  			phb->flags &= ~PNV_PHB_FLAG_EEH;
161  	}
162  }
163  
164  /**
165   * pnv_eeh_post_init - EEH platform dependent post initialization
166   *
167   * EEH platform dependent post initialization on powernv. When
168   * the function is called, the EEH PEs and devices should have
169   * been built. If the I/O cache staff has been built, EEH is
170   * ready to supply service.
171   */
pnv_eeh_post_init(void)172  int pnv_eeh_post_init(void)
173  {
174  	struct pci_controller *hose;
175  	struct pnv_phb *phb;
176  	int ret = 0;
177  
178  	eeh_show_enabled();
179  
180  	/* Register OPAL event notifier */
181  	eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
182  	if (eeh_event_irq < 0) {
183  		pr_err("%s: Can't register OPAL event interrupt (%d)\n",
184  		       __func__, eeh_event_irq);
185  		return eeh_event_irq;
186  	}
187  
188  	ret = request_irq(eeh_event_irq, pnv_eeh_event,
189  			  IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
190  	if (ret < 0) {
191  		irq_dispose_mapping(eeh_event_irq);
192  		pr_err("%s: Can't request OPAL event interrupt (%d)\n",
193  		       __func__, eeh_event_irq);
194  		return ret;
195  	}
196  
197  	if (!eeh_enabled())
198  		disable_irq(eeh_event_irq);
199  
200  	pnv_eeh_enable_phbs();
201  
202  	list_for_each_entry(hose, &hose_list, list_node) {
203  		phb = hose->private_data;
204  
205  		/* Create debugfs entries */
206  #ifdef CONFIG_DEBUG_FS
207  		if (phb->has_dbgfs || !phb->dbgfs)
208  			continue;
209  
210  		phb->has_dbgfs = 1;
211  		debugfs_create_file("err_injct", 0200,
212  				    phb->dbgfs, hose,
213  				    &pnv_eeh_ei_fops);
214  
215  		debugfs_create_file("err_injct_outbound", 0600,
216  				    phb->dbgfs, hose,
217  				    &pnv_eeh_dbgfs_ops_outb);
218  		debugfs_create_file("err_injct_inboundA", 0600,
219  				    phb->dbgfs, hose,
220  				    &pnv_eeh_dbgfs_ops_inbA);
221  		debugfs_create_file("err_injct_inboundB", 0600,
222  				    phb->dbgfs, hose,
223  				    &pnv_eeh_dbgfs_ops_inbB);
224  #endif /* CONFIG_DEBUG_FS */
225  	}
226  
227  	return ret;
228  }
229  
pnv_eeh_find_cap(struct pci_dn * pdn,int cap)230  static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
231  {
232  	int pos = PCI_CAPABILITY_LIST;
233  	int cnt = 48;   /* Maximal number of capabilities */
234  	u32 status, id;
235  
236  	if (!pdn)
237  		return 0;
238  
239  	/* Check if the device supports capabilities */
240  	pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
241  	if (!(status & PCI_STATUS_CAP_LIST))
242  		return 0;
243  
244  	while (cnt--) {
245  		pnv_pci_cfg_read(pdn, pos, 1, &pos);
246  		if (pos < 0x40)
247  			break;
248  
249  		pos &= ~3;
250  		pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
251  		if (id == 0xff)
252  			break;
253  
254  		/* Found */
255  		if (id == cap)
256  			return pos;
257  
258  		/* Next one */
259  		pos += PCI_CAP_LIST_NEXT;
260  	}
261  
262  	return 0;
263  }
264  
pnv_eeh_find_ecap(struct pci_dn * pdn,int cap)265  static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
266  {
267  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
268  	u32 header;
269  	int pos = 256, ttl = (4096 - 256) / 8;
270  
271  	if (!edev || !edev->pcie_cap)
272  		return 0;
273  	if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
274  		return 0;
275  	else if (!header)
276  		return 0;
277  
278  	while (ttl-- > 0) {
279  		if (PCI_EXT_CAP_ID(header) == cap && pos)
280  			return pos;
281  
282  		pos = PCI_EXT_CAP_NEXT(header);
283  		if (pos < 256)
284  			break;
285  
286  		if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
287  			break;
288  	}
289  
290  	return 0;
291  }
292  
pnv_eeh_get_upstream_pe(struct pci_dev * pdev)293  static struct eeh_pe *pnv_eeh_get_upstream_pe(struct pci_dev *pdev)
294  {
295  	struct pci_controller *hose = pdev->bus->sysdata;
296  	struct pnv_phb *phb = hose->private_data;
297  	struct pci_dev *parent = pdev->bus->self;
298  
299  #ifdef CONFIG_PCI_IOV
300  	/* for VFs we use the PF's PE as the upstream PE */
301  	if (pdev->is_virtfn)
302  		parent = pdev->physfn;
303  #endif
304  
305  	/* otherwise use the PE of our parent bridge */
306  	if (parent) {
307  		struct pnv_ioda_pe *ioda_pe = pnv_ioda_get_pe(parent);
308  
309  		return eeh_pe_get(phb->hose, ioda_pe->pe_number);
310  	}
311  
312  	return NULL;
313  }
314  
315  /**
316   * pnv_eeh_probe - Do probe on PCI device
317   * @pdev: pci_dev to probe
318   *
319   * Create, or find the existing, eeh_dev for this pci_dev.
320   */
pnv_eeh_probe(struct pci_dev * pdev)321  static struct eeh_dev *pnv_eeh_probe(struct pci_dev *pdev)
322  {
323  	struct pci_dn *pdn = pci_get_pdn(pdev);
324  	struct pci_controller *hose = pdn->phb;
325  	struct pnv_phb *phb = hose->private_data;
326  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
327  	struct eeh_pe *upstream_pe;
328  	uint32_t pcie_flags;
329  	int ret;
330  	int config_addr = (pdn->busno << 8) | (pdn->devfn);
331  
332  	/*
333  	 * When probing the root bridge, which doesn't have any
334  	 * subordinate PCI devices. We don't have OF node for
335  	 * the root bridge. So it's not reasonable to continue
336  	 * the probing.
337  	 */
338  	if (!edev || edev->pe)
339  		return NULL;
340  
341  	/* already configured? */
342  	if (edev->pdev) {
343  		pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n",
344  			__func__, hose->global_number, config_addr >> 8,
345  			PCI_SLOT(config_addr), PCI_FUNC(config_addr));
346  		return edev;
347  	}
348  
349  	/* Skip for PCI-ISA bridge */
350  	if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
351  		return NULL;
352  
353  	eeh_edev_dbg(edev, "Probing device\n");
354  
355  	/* Initialize eeh device */
356  	edev->mode	&= 0xFFFFFF00;
357  	edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
358  	edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
359  	edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
360  	edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
361  	if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
362  		edev->mode |= EEH_DEV_BRIDGE;
363  		if (edev->pcie_cap) {
364  			pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
365  					 2, &pcie_flags);
366  			pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
367  			if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
368  				edev->mode |= EEH_DEV_ROOT_PORT;
369  			else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
370  				edev->mode |= EEH_DEV_DS_PORT;
371  		}
372  	}
373  
374  	edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
375  
376  	upstream_pe = pnv_eeh_get_upstream_pe(pdev);
377  
378  	/* Create PE */
379  	ret = eeh_pe_tree_insert(edev, upstream_pe);
380  	if (ret) {
381  		eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret);
382  		return NULL;
383  	}
384  
385  	/*
386  	 * If the PE contains any one of following adapters, the
387  	 * PCI config space can't be accessed when dumping EEH log.
388  	 * Otherwise, we will run into fenced PHB caused by shortage
389  	 * of outbound credits in the adapter. The PCI config access
390  	 * should be blocked until PE reset. MMIO access is dropped
391  	 * by hardware certainly. In order to drop PCI config requests,
392  	 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
393  	 * will be checked in the backend for PE state retrieval. If
394  	 * the PE becomes frozen for the first time and the flag has
395  	 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
396  	 * that PE to block its config space.
397  	 *
398  	 * Broadcom BCM5718 2-ports NICs (14e4:1656)
399  	 * Broadcom Austin 4-ports NICs (14e4:1657)
400  	 * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
401  	 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
402  	 */
403  	if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
404  	     pdn->device_id == 0x1656) ||
405  	    (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
406  	     pdn->device_id == 0x1657) ||
407  	    (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
408  	     pdn->device_id == 0x168a) ||
409  	    (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
410  	     pdn->device_id == 0x168e))
411  		edev->pe->state |= EEH_PE_CFG_RESTRICTED;
412  
413  	/*
414  	 * Cache the PE primary bus, which can't be fetched when
415  	 * full hotplug is in progress. In that case, all child
416  	 * PCI devices of the PE are expected to be removed prior
417  	 * to PE reset.
418  	 */
419  	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
420  		edev->pe->bus = pci_find_bus(hose->global_number,
421  					     pdn->busno);
422  		if (edev->pe->bus)
423  			edev->pe->state |= EEH_PE_PRI_BUS;
424  	}
425  
426  	/*
427  	 * Enable EEH explicitly so that we will do EEH check
428  	 * while accessing I/O stuff
429  	 */
430  	if (!eeh_has_flag(EEH_ENABLED)) {
431  		enable_irq(eeh_event_irq);
432  		pnv_eeh_enable_phbs();
433  		eeh_add_flag(EEH_ENABLED);
434  	}
435  
436  	/* Save memory bars */
437  	eeh_save_bars(edev);
438  
439  	eeh_edev_dbg(edev, "EEH enabled on device\n");
440  
441  	return edev;
442  }
443  
444  /**
445   * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
446   * @pe: EEH PE
447   * @option: operation to be issued
448   *
449   * The function is used to control the EEH functionality globally.
450   * Currently, following options are support according to PAPR:
451   * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
452   */
pnv_eeh_set_option(struct eeh_pe * pe,int option)453  static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
454  {
455  	struct pci_controller *hose = pe->phb;
456  	struct pnv_phb *phb = hose->private_data;
457  	bool freeze_pe = false;
458  	int opt;
459  	s64 rc;
460  
461  	switch (option) {
462  	case EEH_OPT_DISABLE:
463  		return -EPERM;
464  	case EEH_OPT_ENABLE:
465  		return 0;
466  	case EEH_OPT_THAW_MMIO:
467  		opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
468  		break;
469  	case EEH_OPT_THAW_DMA:
470  		opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
471  		break;
472  	case EEH_OPT_FREEZE_PE:
473  		freeze_pe = true;
474  		opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
475  		break;
476  	default:
477  		pr_warn("%s: Invalid option %d\n", __func__, option);
478  		return -EINVAL;
479  	}
480  
481  	/* Freeze master and slave PEs if PHB supports compound PEs */
482  	if (freeze_pe) {
483  		if (phb->freeze_pe) {
484  			phb->freeze_pe(phb, pe->addr);
485  			return 0;
486  		}
487  
488  		rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
489  		if (rc != OPAL_SUCCESS) {
490  			pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
491  				__func__, rc, phb->hose->global_number,
492  				pe->addr);
493  			return -EIO;
494  		}
495  
496  		return 0;
497  	}
498  
499  	/* Unfreeze master and slave PEs if PHB supports */
500  	if (phb->unfreeze_pe)
501  		return phb->unfreeze_pe(phb, pe->addr, opt);
502  
503  	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
504  	if (rc != OPAL_SUCCESS) {
505  		pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
506  			__func__, rc, option, phb->hose->global_number,
507  			pe->addr);
508  		return -EIO;
509  	}
510  
511  	return 0;
512  }
513  
pnv_eeh_get_phb_diag(struct eeh_pe * pe)514  static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
515  {
516  	struct pnv_phb *phb = pe->phb->private_data;
517  	s64 rc;
518  
519  	rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
520  					 phb->diag_data_size);
521  	if (rc != OPAL_SUCCESS)
522  		pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
523  			__func__, rc, pe->phb->global_number);
524  }
525  
pnv_eeh_get_phb_state(struct eeh_pe * pe)526  static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
527  {
528  	struct pnv_phb *phb = pe->phb->private_data;
529  	u8 fstate = 0;
530  	__be16 pcierr = 0;
531  	s64 rc;
532  	int result = 0;
533  
534  	rc = opal_pci_eeh_freeze_status(phb->opal_id,
535  					pe->addr,
536  					&fstate,
537  					&pcierr,
538  					NULL);
539  	if (rc != OPAL_SUCCESS) {
540  		pr_warn("%s: Failure %lld getting PHB#%x state\n",
541  			__func__, rc, phb->hose->global_number);
542  		return EEH_STATE_NOT_SUPPORT;
543  	}
544  
545  	/*
546  	 * Check PHB state. If the PHB is frozen for the
547  	 * first time, to dump the PHB diag-data.
548  	 */
549  	if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
550  		result = (EEH_STATE_MMIO_ACTIVE  |
551  			  EEH_STATE_DMA_ACTIVE   |
552  			  EEH_STATE_MMIO_ENABLED |
553  			  EEH_STATE_DMA_ENABLED);
554  	} else if (!(pe->state & EEH_PE_ISOLATED)) {
555  		eeh_pe_mark_isolated(pe);
556  		pnv_eeh_get_phb_diag(pe);
557  
558  		if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
559  			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
560  	}
561  
562  	return result;
563  }
564  
pnv_eeh_get_pe_state(struct eeh_pe * pe)565  static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
566  {
567  	struct pnv_phb *phb = pe->phb->private_data;
568  	u8 fstate = 0;
569  	__be16 pcierr = 0;
570  	s64 rc;
571  	int result;
572  
573  	/*
574  	 * We don't clobber hardware frozen state until PE
575  	 * reset is completed. In order to keep EEH core
576  	 * moving forward, we have to return operational
577  	 * state during PE reset.
578  	 */
579  	if (pe->state & EEH_PE_RESET) {
580  		result = (EEH_STATE_MMIO_ACTIVE  |
581  			  EEH_STATE_DMA_ACTIVE   |
582  			  EEH_STATE_MMIO_ENABLED |
583  			  EEH_STATE_DMA_ENABLED);
584  		return result;
585  	}
586  
587  	/*
588  	 * Fetch PE state from hardware. If the PHB
589  	 * supports compound PE, let it handle that.
590  	 */
591  	if (phb->get_pe_state) {
592  		fstate = phb->get_pe_state(phb, pe->addr);
593  	} else {
594  		rc = opal_pci_eeh_freeze_status(phb->opal_id,
595  						pe->addr,
596  						&fstate,
597  						&pcierr,
598  						NULL);
599  		if (rc != OPAL_SUCCESS) {
600  			pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
601  				__func__, rc, phb->hose->global_number,
602  				pe->addr);
603  			return EEH_STATE_NOT_SUPPORT;
604  		}
605  	}
606  
607  	/* Figure out state */
608  	switch (fstate) {
609  	case OPAL_EEH_STOPPED_NOT_FROZEN:
610  		result = (EEH_STATE_MMIO_ACTIVE  |
611  			  EEH_STATE_DMA_ACTIVE   |
612  			  EEH_STATE_MMIO_ENABLED |
613  			  EEH_STATE_DMA_ENABLED);
614  		break;
615  	case OPAL_EEH_STOPPED_MMIO_FREEZE:
616  		result = (EEH_STATE_DMA_ACTIVE |
617  			  EEH_STATE_DMA_ENABLED);
618  		break;
619  	case OPAL_EEH_STOPPED_DMA_FREEZE:
620  		result = (EEH_STATE_MMIO_ACTIVE |
621  			  EEH_STATE_MMIO_ENABLED);
622  		break;
623  	case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
624  		result = 0;
625  		break;
626  	case OPAL_EEH_STOPPED_RESET:
627  		result = EEH_STATE_RESET_ACTIVE;
628  		break;
629  	case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
630  		result = EEH_STATE_UNAVAILABLE;
631  		break;
632  	case OPAL_EEH_STOPPED_PERM_UNAVAIL:
633  		result = EEH_STATE_NOT_SUPPORT;
634  		break;
635  	default:
636  		result = EEH_STATE_NOT_SUPPORT;
637  		pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
638  			__func__, phb->hose->global_number,
639  			pe->addr, fstate);
640  	}
641  
642  	/*
643  	 * If PHB supports compound PE, to freeze all
644  	 * slave PEs for consistency.
645  	 *
646  	 * If the PE is switching to frozen state for the
647  	 * first time, to dump the PHB diag-data.
648  	 */
649  	if (!(result & EEH_STATE_NOT_SUPPORT) &&
650  	    !(result & EEH_STATE_UNAVAILABLE) &&
651  	    !(result & EEH_STATE_MMIO_ACTIVE) &&
652  	    !(result & EEH_STATE_DMA_ACTIVE)  &&
653  	    !(pe->state & EEH_PE_ISOLATED)) {
654  		if (phb->freeze_pe)
655  			phb->freeze_pe(phb, pe->addr);
656  
657  		eeh_pe_mark_isolated(pe);
658  		pnv_eeh_get_phb_diag(pe);
659  
660  		if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
661  			pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
662  	}
663  
664  	return result;
665  }
666  
667  /**
668   * pnv_eeh_get_state - Retrieve PE state
669   * @pe: EEH PE
670   * @delay: delay while PE state is temporarily unavailable
671   *
672   * Retrieve the state of the specified PE. For IODA-compitable
673   * platform, it should be retrieved from IODA table. Therefore,
674   * we prefer passing down to hardware implementation to handle
675   * it.
676   */
pnv_eeh_get_state(struct eeh_pe * pe,int * delay)677  static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
678  {
679  	int ret;
680  
681  	if (pe->type & EEH_PE_PHB)
682  		ret = pnv_eeh_get_phb_state(pe);
683  	else
684  		ret = pnv_eeh_get_pe_state(pe);
685  
686  	if (!delay)
687  		return ret;
688  
689  	/*
690  	 * If the PE state is temporarily unavailable,
691  	 * to inform the EEH core delay for default
692  	 * period (1 second)
693  	 */
694  	*delay = 0;
695  	if (ret & EEH_STATE_UNAVAILABLE)
696  		*delay = 1000;
697  
698  	return ret;
699  }
700  
pnv_eeh_poll(unsigned long id)701  static s64 pnv_eeh_poll(unsigned long id)
702  {
703  	s64 rc = OPAL_HARDWARE;
704  
705  	while (1) {
706  		rc = opal_pci_poll(id);
707  		if (rc <= 0)
708  			break;
709  
710  		if (system_state < SYSTEM_RUNNING)
711  			udelay(1000 * rc);
712  		else
713  			msleep(rc);
714  	}
715  
716  	return rc;
717  }
718  
pnv_eeh_phb_reset(struct pci_controller * hose,int option)719  int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
720  {
721  	struct pnv_phb *phb = hose->private_data;
722  	s64 rc = OPAL_HARDWARE;
723  
724  	pr_debug("%s: Reset PHB#%x, option=%d\n",
725  		 __func__, hose->global_number, option);
726  
727  	/* Issue PHB complete reset request */
728  	if (option == EEH_RESET_FUNDAMENTAL ||
729  	    option == EEH_RESET_HOT)
730  		rc = opal_pci_reset(phb->opal_id,
731  				    OPAL_RESET_PHB_COMPLETE,
732  				    OPAL_ASSERT_RESET);
733  	else if (option == EEH_RESET_DEACTIVATE)
734  		rc = opal_pci_reset(phb->opal_id,
735  				    OPAL_RESET_PHB_COMPLETE,
736  				    OPAL_DEASSERT_RESET);
737  	if (rc < 0)
738  		goto out;
739  
740  	/*
741  	 * Poll state of the PHB until the request is done
742  	 * successfully. The PHB reset is usually PHB complete
743  	 * reset followed by hot reset on root bus. So we also
744  	 * need the PCI bus settlement delay.
745  	 */
746  	if (rc > 0)
747  		rc = pnv_eeh_poll(phb->opal_id);
748  	if (option == EEH_RESET_DEACTIVATE) {
749  		if (system_state < SYSTEM_RUNNING)
750  			udelay(1000 * EEH_PE_RST_SETTLE_TIME);
751  		else
752  			msleep(EEH_PE_RST_SETTLE_TIME);
753  	}
754  out:
755  	if (rc != OPAL_SUCCESS)
756  		return -EIO;
757  
758  	return 0;
759  }
760  
pnv_eeh_root_reset(struct pci_controller * hose,int option)761  static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
762  {
763  	struct pnv_phb *phb = hose->private_data;
764  	s64 rc = OPAL_HARDWARE;
765  
766  	pr_debug("%s: Reset PHB#%x, option=%d\n",
767  		 __func__, hose->global_number, option);
768  
769  	/*
770  	 * During the reset deassert time, we needn't care
771  	 * the reset scope because the firmware does nothing
772  	 * for fundamental or hot reset during deassert phase.
773  	 */
774  	if (option == EEH_RESET_FUNDAMENTAL)
775  		rc = opal_pci_reset(phb->opal_id,
776  				    OPAL_RESET_PCI_FUNDAMENTAL,
777  				    OPAL_ASSERT_RESET);
778  	else if (option == EEH_RESET_HOT)
779  		rc = opal_pci_reset(phb->opal_id,
780  				    OPAL_RESET_PCI_HOT,
781  				    OPAL_ASSERT_RESET);
782  	else if (option == EEH_RESET_DEACTIVATE)
783  		rc = opal_pci_reset(phb->opal_id,
784  				    OPAL_RESET_PCI_HOT,
785  				    OPAL_DEASSERT_RESET);
786  	if (rc < 0)
787  		goto out;
788  
789  	/* Poll state of the PHB until the request is done */
790  	if (rc > 0)
791  		rc = pnv_eeh_poll(phb->opal_id);
792  	if (option == EEH_RESET_DEACTIVATE)
793  		msleep(EEH_PE_RST_SETTLE_TIME);
794  out:
795  	if (rc != OPAL_SUCCESS)
796  		return -EIO;
797  
798  	return 0;
799  }
800  
__pnv_eeh_bridge_reset(struct pci_dev * dev,int option)801  static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
802  {
803  	struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
804  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
805  	int aer = edev ? edev->aer_cap : 0;
806  	u32 ctrl;
807  
808  	pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n",
809  		 __func__, pci_domain_nr(dev->bus),
810  		 dev->bus->number, option);
811  
812  	switch (option) {
813  	case EEH_RESET_FUNDAMENTAL:
814  	case EEH_RESET_HOT:
815  		/* Don't report linkDown event */
816  		if (aer) {
817  			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
818  					     4, &ctrl);
819  			ctrl |= PCI_ERR_UNC_SURPDN;
820  			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
821  					      4, ctrl);
822  		}
823  
824  		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
825  		ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
826  		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
827  
828  		msleep(EEH_PE_RST_HOLD_TIME);
829  		break;
830  	case EEH_RESET_DEACTIVATE:
831  		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
832  		ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
833  		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);
834  
835  		msleep(EEH_PE_RST_SETTLE_TIME);
836  
837  		/* Continue reporting linkDown event */
838  		if (aer) {
839  			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
840  					     4, &ctrl);
841  			ctrl &= ~PCI_ERR_UNC_SURPDN;
842  			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,
843  					      4, ctrl);
844  		}
845  
846  		break;
847  	}
848  
849  	return 0;
850  }
851  
pnv_eeh_bridge_reset(struct pci_dev * pdev,int option)852  static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
853  {
854  	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
855  	struct pnv_phb *phb = hose->private_data;
856  	struct device_node *dn = pci_device_to_OF_node(pdev);
857  	uint64_t id = PCI_SLOT_ID(phb->opal_id, pci_dev_id(pdev));
858  	uint8_t scope;
859  	int64_t rc;
860  
861  	/* Hot reset to the bus if firmware cannot handle */
862  	if (!dn || !of_property_present(dn, "ibm,reset-by-firmware"))
863  		return __pnv_eeh_bridge_reset(pdev, option);
864  
865  	pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n",
866  		 __func__, pci_domain_nr(pdev->bus),
867  		 pdev->bus->number, option);
868  
869  	switch (option) {
870  	case EEH_RESET_FUNDAMENTAL:
871  		scope = OPAL_RESET_PCI_FUNDAMENTAL;
872  		break;
873  	case EEH_RESET_HOT:
874  		scope = OPAL_RESET_PCI_HOT;
875  		break;
876  	case EEH_RESET_DEACTIVATE:
877  		return 0;
878  	default:
879  		dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
880  			__func__, option);
881  		return -EINVAL;
882  	}
883  
884  	rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
885  	if (rc <= OPAL_SUCCESS)
886  		goto out;
887  
888  	rc = pnv_eeh_poll(id);
889  out:
890  	return (rc == OPAL_SUCCESS) ? 0 : -EIO;
891  }
892  
pnv_pci_reset_secondary_bus(struct pci_dev * dev)893  void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
894  {
895  	struct pci_controller *hose;
896  
897  	if (pci_is_root_bus(dev->bus)) {
898  		hose = pci_bus_to_host(dev->bus);
899  		pnv_eeh_root_reset(hose, EEH_RESET_HOT);
900  		pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
901  	} else {
902  		pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
903  		pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
904  	}
905  }
906  
pnv_eeh_wait_for_pending(struct pci_dn * pdn,const char * type,int pos,u16 mask)907  static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
908  				     int pos, u16 mask)
909  {
910  	struct eeh_dev *edev = pdn->edev;
911  	int i, status = 0;
912  
913  	/* Wait for Transaction Pending bit to be cleared */
914  	for (i = 0; i < 4; i++) {
915  		eeh_ops->read_config(edev, pos, 2, &status);
916  		if (!(status & mask))
917  			return;
918  
919  		msleep((1 << i) * 100);
920  	}
921  
922  	pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
923  		__func__, type,
924  		pdn->phb->global_number, pdn->busno,
925  		PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
926  }
927  
pnv_eeh_do_flr(struct pci_dn * pdn,int option)928  static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
929  {
930  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
931  	u32 reg = 0;
932  
933  	if (WARN_ON(!edev->pcie_cap))
934  		return -ENOTTY;
935  
936  	eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);
937  	if (!(reg & PCI_EXP_DEVCAP_FLR))
938  		return -ENOTTY;
939  
940  	switch (option) {
941  	case EEH_RESET_HOT:
942  	case EEH_RESET_FUNDAMENTAL:
943  		pnv_eeh_wait_for_pending(pdn, "",
944  					 edev->pcie_cap + PCI_EXP_DEVSTA,
945  					 PCI_EXP_DEVSTA_TRPND);
946  		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
947  				     4, &reg);
948  		reg |= PCI_EXP_DEVCTL_BCR_FLR;
949  		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
950  				      4, reg);
951  		msleep(EEH_PE_RST_HOLD_TIME);
952  		break;
953  	case EEH_RESET_DEACTIVATE:
954  		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
955  				     4, &reg);
956  		reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
957  		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
958  				      4, reg);
959  		msleep(EEH_PE_RST_SETTLE_TIME);
960  		break;
961  	}
962  
963  	return 0;
964  }
965  
pnv_eeh_do_af_flr(struct pci_dn * pdn,int option)966  static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
967  {
968  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
969  	u32 cap = 0;
970  
971  	if (WARN_ON(!edev->af_cap))
972  		return -ENOTTY;
973  
974  	eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);
975  	if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
976  		return -ENOTTY;
977  
978  	switch (option) {
979  	case EEH_RESET_HOT:
980  	case EEH_RESET_FUNDAMENTAL:
981  		/*
982  		 * Wait for Transaction Pending bit to clear. A word-aligned
983  		 * test is used, so we use the control offset rather than status
984  		 * and shift the test bit to match.
985  		 */
986  		pnv_eeh_wait_for_pending(pdn, "AF",
987  					 edev->af_cap + PCI_AF_CTRL,
988  					 PCI_AF_STATUS_TP << 8);
989  		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,
990  				      1, PCI_AF_CTRL_FLR);
991  		msleep(EEH_PE_RST_HOLD_TIME);
992  		break;
993  	case EEH_RESET_DEACTIVATE:
994  		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);
995  		msleep(EEH_PE_RST_SETTLE_TIME);
996  		break;
997  	}
998  
999  	return 0;
1000  }
1001  
pnv_eeh_reset_vf_pe(struct eeh_pe * pe,int option)1002  static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1003  {
1004  	struct eeh_dev *edev;
1005  	struct pci_dn *pdn;
1006  	int ret;
1007  
1008  	/* The VF PE should have only one child device */
1009  	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
1010  	pdn = eeh_dev_to_pdn(edev);
1011  	if (!pdn)
1012  		return -ENXIO;
1013  
1014  	ret = pnv_eeh_do_flr(pdn, option);
1015  	if (!ret)
1016  		return ret;
1017  
1018  	return pnv_eeh_do_af_flr(pdn, option);
1019  }
1020  
1021  /**
1022   * pnv_eeh_reset - Reset the specified PE
1023   * @pe: EEH PE
1024   * @option: reset option
1025   *
1026   * Do reset on the indicated PE. For PCI bus sensitive PE,
1027   * we need to reset the parent p2p bridge. The PHB has to
1028   * be reinitialized if the p2p bridge is root bridge. For
1029   * PCI device sensitive PE, we will try to reset the device
1030   * through FLR. For now, we don't have OPAL APIs to do HARD
1031   * reset yet, so all reset would be SOFT (HOT) reset.
1032   */
pnv_eeh_reset(struct eeh_pe * pe,int option)1033  static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1034  {
1035  	struct pci_controller *hose = pe->phb;
1036  	struct pnv_phb *phb;
1037  	struct pci_bus *bus;
1038  	int64_t rc;
1039  
1040  	/*
1041  	 * For PHB reset, we always have complete reset. For those PEs whose
1042  	 * primary bus derived from root complex (root bus) or root port
1043  	 * (usually bus#1), we apply hot or fundamental reset on the root port.
1044  	 * For other PEs, we always have hot reset on the PE primary bus.
1045  	 *
1046  	 * Here, we have different design to pHyp, which always clear the
1047  	 * frozen state during PE reset. However, the good idea here from
1048  	 * benh is to keep frozen state before we get PE reset done completely
1049  	 * (until BAR restore). With the frozen state, HW drops illegal IO
1050  	 * or MMIO access, which can incur recursive frozen PE during PE
1051  	 * reset. The side effect is that EEH core has to clear the frozen
1052  	 * state explicitly after BAR restore.
1053  	 */
1054  	if (pe->type & EEH_PE_PHB)
1055  		return pnv_eeh_phb_reset(hose, option);
1056  
1057  	/*
1058  	 * The frozen PE might be caused by PAPR error injection
1059  	 * registers, which are expected to be cleared after hitting
1060  	 * frozen PE as stated in the hardware spec. Unfortunately,
1061  	 * that's not true on P7IOC. So we have to clear it manually
1062  	 * to avoid recursive EEH errors during recovery.
1063  	 */
1064  	phb = hose->private_data;
1065  	if (phb->model == PNV_PHB_MODEL_P7IOC &&
1066  	    (option == EEH_RESET_HOT ||
1067  	     option == EEH_RESET_FUNDAMENTAL)) {
1068  		rc = opal_pci_reset(phb->opal_id,
1069  				    OPAL_RESET_PHB_ERROR,
1070  				    OPAL_ASSERT_RESET);
1071  		if (rc != OPAL_SUCCESS) {
1072  			pr_warn("%s: Failure %lld clearing error injection registers\n",
1073  				__func__, rc);
1074  			return -EIO;
1075  		}
1076  	}
1077  
1078  	if (pe->type & EEH_PE_VF)
1079  		return pnv_eeh_reset_vf_pe(pe, option);
1080  
1081  	bus = eeh_pe_bus_get(pe);
1082  	if (!bus) {
1083  		pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n",
1084  			__func__, pe->phb->global_number, pe->addr);
1085  		return -EIO;
1086  	}
1087  
1088  	if (pci_is_root_bus(bus))
1089  		return pnv_eeh_root_reset(hose, option);
1090  
1091  	/*
1092  	 * For hot resets try use the generic PCI error recovery reset
1093  	 * functions. These correctly handles the case where the secondary
1094  	 * bus is behind a hotplug slot and it will use the slot provided
1095  	 * reset methods to prevent spurious hotplug events during the reset.
1096  	 *
1097  	 * Fundamental resets need to be handled internally to EEH since the
1098  	 * PCI core doesn't really have a concept of a fundamental reset,
1099  	 * mainly because there's no standard way to generate one. Only a
1100  	 * few devices require an FRESET so it should be fine.
1101  	 */
1102  	if (option != EEH_RESET_FUNDAMENTAL) {
1103  		/*
1104  		 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the
1105  		 *     de-assert step. It's like the OPAL reset API was
1106  		 *     poorly designed or something...
1107  		 */
1108  		if (option == EEH_RESET_DEACTIVATE)
1109  			return 0;
1110  
1111  		rc = pci_bus_error_reset(bus->self);
1112  		if (!rc)
1113  			return 0;
1114  	}
1115  
1116  	/* otherwise, use the generic bridge reset. this might call into FW */
1117  	if (pci_is_root_bus(bus->parent))
1118  		return pnv_eeh_root_reset(hose, option);
1119  	return pnv_eeh_bridge_reset(bus->self, option);
1120  }
1121  
1122  /**
1123   * pnv_eeh_get_log - Retrieve error log
1124   * @pe: EEH PE
1125   * @severity: temporary or permanent error log
1126   * @drv_log: driver log to be combined with retrieved error log
1127   * @len: length of driver log
1128   *
1129   * Retrieve the temporary or permanent error from the PE.
1130   */
pnv_eeh_get_log(struct eeh_pe * pe,int severity,char * drv_log,unsigned long len)1131  static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1132  			   char *drv_log, unsigned long len)
1133  {
1134  	if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1135  		pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1136  
1137  	return 0;
1138  }
1139  
1140  /**
1141   * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1142   * @pe: EEH PE
1143   *
1144   * The function will be called to reconfigure the bridges included
1145   * in the specified PE so that the mulfunctional PE would be recovered
1146   * again.
1147   */
pnv_eeh_configure_bridge(struct eeh_pe * pe)1148  static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1149  {
1150  	return 0;
1151  }
1152  
1153  /**
1154   * pnv_pe_err_inject - Inject specified error to the indicated PE
1155   * @pe: the indicated PE
1156   * @type: error type
1157   * @func: specific error type
1158   * @addr: address
1159   * @mask: address mask
1160   *
1161   * The routine is called to inject specified error, which is
1162   * determined by @type and @func, to the indicated PE for
1163   * testing purpose.
1164   */
pnv_eeh_err_inject(struct eeh_pe * pe,int type,int func,unsigned long addr,unsigned long mask)1165  static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1166  			      unsigned long addr, unsigned long mask)
1167  {
1168  	struct pci_controller *hose = pe->phb;
1169  	struct pnv_phb *phb = hose->private_data;
1170  	s64 rc;
1171  
1172  	if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1173  	    type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1174  		pr_warn("%s: Invalid error type %d\n",
1175  			__func__, type);
1176  		return -ERANGE;
1177  	}
1178  
1179  	if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1180  	    func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1181  		pr_warn("%s: Invalid error function %d\n",
1182  			__func__, func);
1183  		return -ERANGE;
1184  	}
1185  
1186  	/* Firmware supports error injection ? */
1187  	if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1188  		pr_warn("%s: Firmware doesn't support error injection\n",
1189  			__func__);
1190  		return -ENXIO;
1191  	}
1192  
1193  	/* Do error injection */
1194  	rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1195  				 type, func, addr, mask);
1196  	if (rc != OPAL_SUCCESS) {
1197  		pr_warn("%s: Failure %lld injecting error "
1198  			"%d-%d to PHB#%x-PE#%x\n",
1199  			__func__, rc, type, func,
1200  			hose->global_number, pe->addr);
1201  		return -EIO;
1202  	}
1203  
1204  	return 0;
1205  }
1206  
pnv_eeh_cfg_blocked(struct pci_dn * pdn)1207  static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1208  {
1209  	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1210  
1211  	if (!edev || !edev->pe)
1212  		return false;
1213  
1214  	/*
1215  	 * We will issue FLR or AF FLR to all VFs, which are contained
1216  	 * in VF PE. It relies on the EEH PCI config accessors. So we
1217  	 * can't block them during the window.
1218  	 */
1219  	if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1220  		return false;
1221  
1222  	if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1223  		return true;
1224  
1225  	return false;
1226  }
1227  
pnv_eeh_read_config(struct eeh_dev * edev,int where,int size,u32 * val)1228  static int pnv_eeh_read_config(struct eeh_dev *edev,
1229  			       int where, int size, u32 *val)
1230  {
1231  	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
1232  
1233  	if (!pdn)
1234  		return PCIBIOS_DEVICE_NOT_FOUND;
1235  
1236  	if (pnv_eeh_cfg_blocked(pdn)) {
1237  		*val = 0xFFFFFFFF;
1238  		return PCIBIOS_SET_FAILED;
1239  	}
1240  
1241  	return pnv_pci_cfg_read(pdn, where, size, val);
1242  }
1243  
pnv_eeh_write_config(struct eeh_dev * edev,int where,int size,u32 val)1244  static int pnv_eeh_write_config(struct eeh_dev *edev,
1245  				int where, int size, u32 val)
1246  {
1247  	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
1248  
1249  	if (!pdn)
1250  		return PCIBIOS_DEVICE_NOT_FOUND;
1251  
1252  	if (pnv_eeh_cfg_blocked(pdn))
1253  		return PCIBIOS_SET_FAILED;
1254  
1255  	return pnv_pci_cfg_write(pdn, where, size, val);
1256  }
1257  
pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData * data)1258  static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1259  {
1260  	/* GEM */
1261  	if (data->gemXfir || data->gemRfir ||
1262  	    data->gemRirqfir || data->gemMask || data->gemRwof)
1263  		pr_info("  GEM: %016llx %016llx %016llx %016llx %016llx\n",
1264  			be64_to_cpu(data->gemXfir),
1265  			be64_to_cpu(data->gemRfir),
1266  			be64_to_cpu(data->gemRirqfir),
1267  			be64_to_cpu(data->gemMask),
1268  			be64_to_cpu(data->gemRwof));
1269  
1270  	/* LEM */
1271  	if (data->lemFir || data->lemErrMask ||
1272  	    data->lemAction0 || data->lemAction1 || data->lemWof)
1273  		pr_info("  LEM: %016llx %016llx %016llx %016llx %016llx\n",
1274  			be64_to_cpu(data->lemFir),
1275  			be64_to_cpu(data->lemErrMask),
1276  			be64_to_cpu(data->lemAction0),
1277  			be64_to_cpu(data->lemAction1),
1278  			be64_to_cpu(data->lemWof));
1279  }
1280  
pnv_eeh_get_and_dump_hub_diag(struct pci_controller * hose)1281  static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1282  {
1283  	struct pnv_phb *phb = hose->private_data;
1284  	struct OpalIoP7IOCErrorData *data =
1285  		(struct OpalIoP7IOCErrorData*)phb->diag_data;
1286  	long rc;
1287  
1288  	rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1289  	if (rc != OPAL_SUCCESS) {
1290  		pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1291  			__func__, phb->hub_id, rc);
1292  		return;
1293  	}
1294  
1295  	switch (be16_to_cpu(data->type)) {
1296  	case OPAL_P7IOC_DIAG_TYPE_RGC:
1297  		pr_info("P7IOC diag-data for RGC\n\n");
1298  		pnv_eeh_dump_hub_diag_common(data);
1299  		if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1300  			pr_info("  RGC: %016llx %016llx\n",
1301  				be64_to_cpu(data->rgc.rgcStatus),
1302  				be64_to_cpu(data->rgc.rgcLdcp));
1303  		break;
1304  	case OPAL_P7IOC_DIAG_TYPE_BI:
1305  		pr_info("P7IOC diag-data for BI %s\n\n",
1306  			data->bi.biDownbound ? "Downbound" : "Upbound");
1307  		pnv_eeh_dump_hub_diag_common(data);
1308  		if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1309  		    data->bi.biLdcp2 || data->bi.biFenceStatus)
1310  			pr_info("  BI:  %016llx %016llx %016llx %016llx\n",
1311  				be64_to_cpu(data->bi.biLdcp0),
1312  				be64_to_cpu(data->bi.biLdcp1),
1313  				be64_to_cpu(data->bi.biLdcp2),
1314  				be64_to_cpu(data->bi.biFenceStatus));
1315  		break;
1316  	case OPAL_P7IOC_DIAG_TYPE_CI:
1317  		pr_info("P7IOC diag-data for CI Port %d\n\n",
1318  			data->ci.ciPort);
1319  		pnv_eeh_dump_hub_diag_common(data);
1320  		if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1321  			pr_info("  CI:  %016llx %016llx\n",
1322  				be64_to_cpu(data->ci.ciPortStatus),
1323  				be64_to_cpu(data->ci.ciPortLdcp));
1324  		break;
1325  	case OPAL_P7IOC_DIAG_TYPE_MISC:
1326  		pr_info("P7IOC diag-data for MISC\n\n");
1327  		pnv_eeh_dump_hub_diag_common(data);
1328  		break;
1329  	case OPAL_P7IOC_DIAG_TYPE_I2C:
1330  		pr_info("P7IOC diag-data for I2C\n\n");
1331  		pnv_eeh_dump_hub_diag_common(data);
1332  		break;
1333  	default:
1334  		pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1335  			__func__, phb->hub_id, data->type);
1336  	}
1337  }
1338  
pnv_eeh_get_pe(struct pci_controller * hose,u16 pe_no,struct eeh_pe ** pe)1339  static int pnv_eeh_get_pe(struct pci_controller *hose,
1340  			  u16 pe_no, struct eeh_pe **pe)
1341  {
1342  	struct pnv_phb *phb = hose->private_data;
1343  	struct pnv_ioda_pe *pnv_pe;
1344  	struct eeh_pe *dev_pe;
1345  
1346  	/*
1347  	 * If PHB supports compound PE, to fetch
1348  	 * the master PE because slave PE is invisible
1349  	 * to EEH core.
1350  	 */
1351  	pnv_pe = &phb->ioda.pe_array[pe_no];
1352  	if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1353  		pnv_pe = pnv_pe->master;
1354  		WARN_ON(!pnv_pe ||
1355  			!(pnv_pe->flags & PNV_IODA_PE_MASTER));
1356  		pe_no = pnv_pe->pe_number;
1357  	}
1358  
1359  	/* Find the PE according to PE# */
1360  	dev_pe = eeh_pe_get(hose, pe_no);
1361  	if (!dev_pe)
1362  		return -EEXIST;
1363  
1364  	/* Freeze the (compound) PE */
1365  	*pe = dev_pe;
1366  	if (!(dev_pe->state & EEH_PE_ISOLATED))
1367  		phb->freeze_pe(phb, pe_no);
1368  
1369  	/*
1370  	 * At this point, we're sure the (compound) PE should
1371  	 * have been frozen. However, we still need poke until
1372  	 * hitting the frozen PE on top level.
1373  	 */
1374  	dev_pe = dev_pe->parent;
1375  	while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1376  		int ret;
1377  		ret = eeh_ops->get_state(dev_pe, NULL);
1378  		if (ret <= 0 || eeh_state_active(ret)) {
1379  			dev_pe = dev_pe->parent;
1380  			continue;
1381  		}
1382  
1383  		/* Frozen parent PE */
1384  		*pe = dev_pe;
1385  		if (!(dev_pe->state & EEH_PE_ISOLATED))
1386  			phb->freeze_pe(phb, dev_pe->addr);
1387  
1388  		/* Next one */
1389  		dev_pe = dev_pe->parent;
1390  	}
1391  
1392  	return 0;
1393  }
1394  
1395  /**
1396   * pnv_eeh_next_error - Retrieve next EEH error to handle
1397   * @pe: Affected PE
1398   *
1399   * The function is expected to be called by EEH core while it gets
1400   * special EEH event (without binding PE). The function calls to
1401   * OPAL APIs for next error to handle. The informational error is
1402   * handled internally by platform. However, the dead IOC, dead PHB,
1403   * fenced PHB and frozen PE should be handled by EEH core eventually.
1404   */
pnv_eeh_next_error(struct eeh_pe ** pe)1405  static int pnv_eeh_next_error(struct eeh_pe **pe)
1406  {
1407  	struct pci_controller *hose;
1408  	struct pnv_phb *phb;
1409  	struct eeh_pe *phb_pe, *parent_pe;
1410  	__be64 frozen_pe_no;
1411  	__be16 err_type, severity;
1412  	long rc;
1413  	int state, ret = EEH_NEXT_ERR_NONE;
1414  
1415  	/*
1416  	 * While running here, it's safe to purge the event queue. The
1417  	 * event should still be masked.
1418  	 */
1419  	eeh_remove_event(NULL, false);
1420  
1421  	list_for_each_entry(hose, &hose_list, list_node) {
1422  		/*
1423  		 * If the subordinate PCI buses of the PHB has been
1424  		 * removed or is exactly under error recovery, we
1425  		 * needn't take care of it any more.
1426  		 */
1427  		phb = hose->private_data;
1428  		phb_pe = eeh_phb_pe_get(hose);
1429  		if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1430  			continue;
1431  
1432  		rc = opal_pci_next_error(phb->opal_id,
1433  					 &frozen_pe_no, &err_type, &severity);
1434  		if (rc != OPAL_SUCCESS) {
1435  			pr_devel("%s: Invalid return value on "
1436  				 "PHB#%x (0x%lx) from opal_pci_next_error",
1437  				 __func__, hose->global_number, rc);
1438  			continue;
1439  		}
1440  
1441  		/* If the PHB doesn't have error, stop processing */
1442  		if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1443  		    be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1444  			pr_devel("%s: No error found on PHB#%x\n",
1445  				 __func__, hose->global_number);
1446  			continue;
1447  		}
1448  
1449  		/*
1450  		 * Processing the error. We're expecting the error with
1451  		 * highest priority reported upon multiple errors on the
1452  		 * specific PHB.
1453  		 */
1454  		pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1455  			__func__, be16_to_cpu(err_type),
1456  			be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1457  			hose->global_number);
1458  		switch (be16_to_cpu(err_type)) {
1459  		case OPAL_EEH_IOC_ERROR:
1460  			if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1461  				pr_err("EEH: dead IOC detected\n");
1462  				ret = EEH_NEXT_ERR_DEAD_IOC;
1463  			} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1464  				pr_info("EEH: IOC informative error "
1465  					"detected\n");
1466  				pnv_eeh_get_and_dump_hub_diag(hose);
1467  				ret = EEH_NEXT_ERR_NONE;
1468  			}
1469  
1470  			break;
1471  		case OPAL_EEH_PHB_ERROR:
1472  			if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1473  				*pe = phb_pe;
1474  				pr_err("EEH: dead PHB#%x detected, "
1475  				       "location: %s\n",
1476  					hose->global_number,
1477  					eeh_pe_loc_get(phb_pe));
1478  				ret = EEH_NEXT_ERR_DEAD_PHB;
1479  			} else if (be16_to_cpu(severity) ==
1480  				   OPAL_EEH_SEV_PHB_FENCED) {
1481  				*pe = phb_pe;
1482  				pr_err("EEH: Fenced PHB#%x detected, "
1483  				       "location: %s\n",
1484  					hose->global_number,
1485  					eeh_pe_loc_get(phb_pe));
1486  				ret = EEH_NEXT_ERR_FENCED_PHB;
1487  			} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1488  				pr_info("EEH: PHB#%x informative error "
1489  					"detected, location: %s\n",
1490  					hose->global_number,
1491  					eeh_pe_loc_get(phb_pe));
1492  				pnv_eeh_get_phb_diag(phb_pe);
1493  				pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1494  				ret = EEH_NEXT_ERR_NONE;
1495  			}
1496  
1497  			break;
1498  		case OPAL_EEH_PE_ERROR:
1499  			/*
1500  			 * If we can't find the corresponding PE, we
1501  			 * just try to unfreeze.
1502  			 */
1503  			if (pnv_eeh_get_pe(hose,
1504  				be64_to_cpu(frozen_pe_no), pe)) {
1505  				pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1506  					hose->global_number, be64_to_cpu(frozen_pe_no));
1507  				pr_info("EEH: PHB location: %s\n",
1508  					eeh_pe_loc_get(phb_pe));
1509  
1510  				/* Dump PHB diag-data */
1511  				rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1512  					phb->diag_data, phb->diag_data_size);
1513  				if (rc == OPAL_SUCCESS)
1514  					pnv_pci_dump_phb_diag_data(hose,
1515  							phb->diag_data);
1516  
1517  				/* Try best to clear it */
1518  				opal_pci_eeh_freeze_clear(phb->opal_id,
1519  					be64_to_cpu(frozen_pe_no),
1520  					OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1521  				ret = EEH_NEXT_ERR_NONE;
1522  			} else if ((*pe)->state & EEH_PE_ISOLATED ||
1523  				   eeh_pe_passed(*pe)) {
1524  				ret = EEH_NEXT_ERR_NONE;
1525  			} else {
1526  				pr_err("EEH: Frozen PE#%x "
1527  				       "on PHB#%x detected\n",
1528  				       (*pe)->addr,
1529  					(*pe)->phb->global_number);
1530  				pr_err("EEH: PE location: %s, "
1531  				       "PHB location: %s\n",
1532  				       eeh_pe_loc_get(*pe),
1533  				       eeh_pe_loc_get(phb_pe));
1534  				ret = EEH_NEXT_ERR_FROZEN_PE;
1535  			}
1536  
1537  			break;
1538  		default:
1539  			pr_warn("%s: Unexpected error type %d\n",
1540  				__func__, be16_to_cpu(err_type));
1541  		}
1542  
1543  		/*
1544  		 * EEH core will try recover from fenced PHB or
1545  		 * frozen PE. In the time for frozen PE, EEH core
1546  		 * enable IO path for that before collecting logs,
1547  		 * but it ruins the site. So we have to dump the
1548  		 * log in advance here.
1549  		 */
1550  		if ((ret == EEH_NEXT_ERR_FROZEN_PE  ||
1551  		    ret == EEH_NEXT_ERR_FENCED_PHB) &&
1552  		    !((*pe)->state & EEH_PE_ISOLATED)) {
1553  			eeh_pe_mark_isolated(*pe);
1554  			pnv_eeh_get_phb_diag(*pe);
1555  
1556  			if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1557  				pnv_pci_dump_phb_diag_data((*pe)->phb,
1558  							   (*pe)->data);
1559  		}
1560  
1561  		/*
1562  		 * We probably have the frozen parent PE out there and
1563  		 * we need have to handle frozen parent PE firstly.
1564  		 */
1565  		if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1566  			parent_pe = (*pe)->parent;
1567  			while (parent_pe) {
1568  				/* Hit the ceiling ? */
1569  				if (parent_pe->type & EEH_PE_PHB)
1570  					break;
1571  
1572  				/* Frozen parent PE ? */
1573  				state = eeh_ops->get_state(parent_pe, NULL);
1574  				if (state > 0 && !eeh_state_active(state))
1575  					*pe = parent_pe;
1576  
1577  				/* Next parent level */
1578  				parent_pe = parent_pe->parent;
1579  			}
1580  
1581  			/* We possibly migrate to another PE */
1582  			eeh_pe_mark_isolated(*pe);
1583  		}
1584  
1585  		/*
1586  		 * If we have no errors on the specific PHB or only
1587  		 * informative error there, we continue poking it.
1588  		 * Otherwise, we need actions to be taken by upper
1589  		 * layer.
1590  		 */
1591  		if (ret > EEH_NEXT_ERR_INF)
1592  			break;
1593  	}
1594  
1595  	/* Unmask the event */
1596  	if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1597  		enable_irq(eeh_event_irq);
1598  
1599  	return ret;
1600  }
1601  
pnv_eeh_restore_config(struct eeh_dev * edev)1602  static int pnv_eeh_restore_config(struct eeh_dev *edev)
1603  {
1604  	struct pnv_phb *phb;
1605  	s64 ret = 0;
1606  
1607  	if (!edev)
1608  		return -EEXIST;
1609  
1610  	if (edev->physfn)
1611  		return 0;
1612  
1613  	phb = edev->controller->private_data;
1614  	ret = opal_pci_reinit(phb->opal_id,
1615  			      OPAL_REINIT_PCI_DEV, edev->bdfn);
1616  
1617  	if (ret) {
1618  		pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1619  			__func__, edev->bdfn, ret);
1620  		return -EIO;
1621  	}
1622  
1623  	return ret;
1624  }
1625  
1626  static struct eeh_ops pnv_eeh_ops = {
1627  	.name                   = "powernv",
1628  	.probe			= pnv_eeh_probe,
1629  	.set_option             = pnv_eeh_set_option,
1630  	.get_state              = pnv_eeh_get_state,
1631  	.reset                  = pnv_eeh_reset,
1632  	.get_log                = pnv_eeh_get_log,
1633  	.configure_bridge       = pnv_eeh_configure_bridge,
1634  	.err_inject		= pnv_eeh_err_inject,
1635  	.read_config            = pnv_eeh_read_config,
1636  	.write_config           = pnv_eeh_write_config,
1637  	.next_error		= pnv_eeh_next_error,
1638  	.restore_config		= pnv_eeh_restore_config,
1639  	.notify_resume		= NULL
1640  };
1641  
1642  /**
1643   * eeh_powernv_init - Register platform dependent EEH operations
1644   *
1645   * EEH initialization on powernv platform. This function should be
1646   * called before any EEH related functions.
1647   */
eeh_powernv_init(void)1648  static int __init eeh_powernv_init(void)
1649  {
1650  	int max_diag_size = PNV_PCI_DIAG_BUF_SIZE;
1651  	struct pci_controller *hose;
1652  	struct pnv_phb *phb;
1653  	int ret = -EINVAL;
1654  
1655  	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
1656  		pr_warn("%s: OPAL is required !\n", __func__);
1657  		return -EINVAL;
1658  	}
1659  
1660  	/* Set probe mode */
1661  	eeh_add_flag(EEH_PROBE_MODE_DEV);
1662  
1663  	/*
1664  	 * P7IOC blocks PCI config access to frozen PE, but PHB3
1665  	 * doesn't do that. So we have to selectively enable I/O
1666  	 * prior to collecting error log.
1667  	 */
1668  	list_for_each_entry(hose, &hose_list, list_node) {
1669  		phb = hose->private_data;
1670  
1671  		if (phb->model == PNV_PHB_MODEL_P7IOC)
1672  			eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
1673  
1674  		if (phb->diag_data_size > max_diag_size)
1675  			max_diag_size = phb->diag_data_size;
1676  
1677  		break;
1678  	}
1679  
1680  	/*
1681  	 * eeh_init() allocates the eeh_pe and its aux data buf so the
1682  	 * size needs to be set before calling eeh_init().
1683  	 */
1684  	eeh_set_pe_aux_size(max_diag_size);
1685  	ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device;
1686  
1687  	ret = eeh_init(&pnv_eeh_ops);
1688  	if (!ret)
1689  		pr_info("EEH: PowerNV platform initialized\n");
1690  	else
1691  		pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1692  
1693  	return ret;
1694  }
1695  machine_arch_initcall(powernv, eeh_powernv_init);
1696