1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #include <linux/cpu.h>
8 #include <linux/delay.h>
9 #include <linux/io.h>
10 #include <linux/memblock.h>
11 #include <linux/sched/task_stack.h>
12 #include <linux/sched/hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/smp.h>
15 #include <linux/types.h>
16 #include <linux/irq.h>
17
18 #include <asm/bcache.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mips_mt.h>
21 #include <asm/mipsregs.h>
22 #include <asm/pm-cps.h>
23 #include <asm/r4kcache.h>
24 #include <asm/regdef.h>
25 #include <asm/smp.h>
26 #include <asm/smp-cps.h>
27 #include <asm/time.h>
28 #include <asm/uasm.h>
29
30 #define BEV_VEC_SIZE 0x500
31 #define BEV_VEC_ALIGN 0x1000
32
33 enum label_id {
34 label_not_nmi = 1,
35 };
36
37 UASM_L_LA(_not_nmi)
38
39 static DECLARE_BITMAP(core_power, NR_CPUS);
40 static uint32_t core_entry_reg;
41 static phys_addr_t cps_vec_pa;
42
43 struct core_boot_config *mips_cps_core_bootcfg;
44
core_vpe_count(unsigned int cluster,unsigned core)45 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
46 {
47 return min(smp_max_threads, mips_cps_numvps(cluster, core));
48 }
49
mips_cps_build_core_entry(void * addr)50 static void __init *mips_cps_build_core_entry(void *addr)
51 {
52 extern void (*nmi_handler)(void);
53 u32 *p = addr;
54 u32 val;
55 struct uasm_label labels[2];
56 struct uasm_reloc relocs[2];
57 struct uasm_label *l = labels;
58 struct uasm_reloc *r = relocs;
59
60 memset(labels, 0, sizeof(labels));
61 memset(relocs, 0, sizeof(relocs));
62
63 uasm_i_mfc0(&p, GPR_K0, C0_STATUS);
64 UASM_i_LA(&p, GPR_T9, ST0_NMI);
65 uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9);
66
67 uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi);
68 uasm_i_nop(&p);
69 UASM_i_LA(&p, GPR_K0, (long)&nmi_handler);
70
71 uasm_l_not_nmi(&l, p);
72
73 val = CAUSEF_IV;
74 uasm_i_lui(&p, GPR_K0, val >> 16);
75 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
76 uasm_i_mtc0(&p, GPR_K0, C0_CAUSE);
77 val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64;
78 uasm_i_lui(&p, GPR_K0, val >> 16);
79 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff);
80 uasm_i_mtc0(&p, GPR_K0, C0_STATUS);
81 uasm_i_ehb(&p);
82 uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK);
83 UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base);
84 #if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT)
85 UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot)));
86 #else
87 UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot)));
88 #endif
89 uasm_i_jr(&p, GPR_T9);
90 uasm_i_nop(&p);
91
92 uasm_resolve_relocs(relocs, labels);
93
94 return p;
95 }
96
allocate_cps_vecs(void)97 static int __init allocate_cps_vecs(void)
98 {
99 /* Try to allocate in KSEG1 first */
100 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
101 0x0, CSEGX_SIZE - 1);
102
103 if (cps_vec_pa)
104 core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
105 CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
106
107 if (!cps_vec_pa && mips_cm_is64) {
108 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
109 0x0, SZ_4G - 1);
110 if (cps_vec_pa)
111 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
112 CM_GCR_Cx_RESET_BASE_MODE;
113 }
114
115 if (!cps_vec_pa)
116 return -ENOMEM;
117
118 return 0;
119 }
120
setup_cps_vecs(void)121 static void __init setup_cps_vecs(void)
122 {
123 void *cps_vec;
124
125 cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa);
126 mips_cps_build_core_entry(cps_vec);
127
128 memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80);
129 memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80);
130 memcpy(cps_vec + 0x300, &excep_cache, 0x80);
131 memcpy(cps_vec + 0x380, &excep_genex, 0x80);
132 memcpy(cps_vec + 0x400, &excep_intex, 0x80);
133 memcpy(cps_vec + 0x480, &excep_ejtag, 0x80);
134
135 /* Make sure no prefetched data in cache */
136 blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE);
137 bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE);
138 __sync();
139 }
140
cps_smp_setup(void)141 static void __init cps_smp_setup(void)
142 {
143 unsigned int nclusters, ncores, nvpes, core_vpes;
144 int cl, c, v;
145
146 /* Detect & record VPE topology */
147 nvpes = 0;
148 nclusters = mips_cps_numclusters();
149 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
150 for (cl = 0; cl < nclusters; cl++) {
151 if (cl > 0)
152 pr_cont(",");
153 pr_cont("{");
154
155 ncores = mips_cps_numcores(cl);
156 for (c = 0; c < ncores; c++) {
157 core_vpes = core_vpe_count(cl, c);
158
159 if (c > 0)
160 pr_cont(",");
161 pr_cont("%u", core_vpes);
162
163 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
164 if (!cl && !c)
165 smp_num_siblings = core_vpes;
166
167 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
168 cpu_set_cluster(&cpu_data[nvpes + v], cl);
169 cpu_set_core(&cpu_data[nvpes + v], c);
170 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
171 }
172
173 nvpes += core_vpes;
174 }
175
176 pr_cont("}");
177 }
178 pr_cont(" total %u\n", nvpes);
179
180 /* Indicate present CPUs (CPU being synonymous with VPE) */
181 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
182 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
183 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
184 __cpu_number_map[v] = v;
185 __cpu_logical_map[v] = v;
186 }
187
188 /* Set a coherent default CCA (CWB) */
189 change_c0_config(CONF_CM_CMASK, 0x5);
190
191 /* Core 0 is powered up (we're running on it) */
192 bitmap_set(core_power, 0, 1);
193
194 /* Initialise core 0 */
195 mips_cps_core_init();
196
197 /* Make core 0 coherent with everything */
198 write_gcr_cl_coherence(0xff);
199
200 if (allocate_cps_vecs())
201 pr_err("Failed to allocate CPS vectors\n");
202
203 if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3)
204 write_gcr_bev_base(core_entry_reg);
205
206 #ifdef CONFIG_MIPS_MT_FPAFF
207 /* If we have an FPU, enroll ourselves in the FPU-full mask */
208 if (cpu_has_fpu)
209 cpumask_set_cpu(0, &mt_fpu_cpumask);
210 #endif /* CONFIG_MIPS_MT_FPAFF */
211 }
212
cps_prepare_cpus(unsigned int max_cpus)213 static void __init cps_prepare_cpus(unsigned int max_cpus)
214 {
215 unsigned ncores, core_vpes, c, cca;
216 bool cca_unsuitable, cores_limited;
217
218 mips_mt_set_cpuoptions();
219
220 if (!core_entry_reg) {
221 pr_err("core_entry address unsuitable, disabling smp-cps\n");
222 goto err_out;
223 }
224
225 /* Detect whether the CCA is unsuited to multi-core SMP */
226 cca = read_c0_config() & CONF_CM_CMASK;
227 switch (cca) {
228 case 0x4: /* CWBE */
229 case 0x5: /* CWB */
230 /* The CCA is coherent, multi-core is fine */
231 cca_unsuitable = false;
232 break;
233
234 default:
235 /* CCA is not coherent, multi-core is not usable */
236 cca_unsuitable = true;
237 }
238
239 /* Warn the user if the CCA prevents multi-core */
240 cores_limited = false;
241 if (cca_unsuitable || cpu_has_dc_aliases) {
242 for_each_present_cpu(c) {
243 if (cpus_are_siblings(smp_processor_id(), c))
244 continue;
245
246 set_cpu_present(c, false);
247 cores_limited = true;
248 }
249 }
250 if (cores_limited)
251 pr_warn("Using only one core due to %s%s%s\n",
252 cca_unsuitable ? "unsuitable CCA" : "",
253 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
254 cpu_has_dc_aliases ? "dcache aliasing" : "");
255
256 setup_cps_vecs();
257
258 /* Allocate core boot configuration structs */
259 ncores = mips_cps_numcores(0);
260 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
261 GFP_KERNEL);
262 if (!mips_cps_core_bootcfg) {
263 pr_err("Failed to allocate boot config for %u cores\n", ncores);
264 goto err_out;
265 }
266
267 /* Allocate VPE boot configuration structs */
268 for (c = 0; c < ncores; c++) {
269 core_vpes = core_vpe_count(0, c);
270 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
271 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
272 GFP_KERNEL);
273 if (!mips_cps_core_bootcfg[c].vpe_config) {
274 pr_err("Failed to allocate %u VPE boot configs\n",
275 core_vpes);
276 goto err_out;
277 }
278 }
279
280 /* Mark this CPU as booted */
281 atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
282 1 << cpu_vpe_id(¤t_cpu_data));
283
284 return;
285 err_out:
286 /* Clean up allocations */
287 if (mips_cps_core_bootcfg) {
288 for (c = 0; c < ncores; c++)
289 kfree(mips_cps_core_bootcfg[c].vpe_config);
290 kfree(mips_cps_core_bootcfg);
291 mips_cps_core_bootcfg = NULL;
292 }
293
294 /* Effectively disable SMP by declaring CPUs not present */
295 for_each_possible_cpu(c) {
296 if (c == 0)
297 continue;
298 set_cpu_present(c, false);
299 }
300 }
301
boot_core(unsigned int core,unsigned int vpe_id)302 static void boot_core(unsigned int core, unsigned int vpe_id)
303 {
304 u32 stat, seq_state;
305 unsigned timeout;
306
307 /* Select the appropriate core */
308 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
309
310 /* Set its reset vector */
311 write_gcr_co_reset_base(core_entry_reg);
312
313 /* Ensure its coherency is disabled */
314 write_gcr_co_coherence(0);
315
316 /* Start it with the legacy memory map and exception base */
317 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
318
319 /* Ensure the core can access the GCRs */
320 if (mips_cm_revision() < CM_REV_CM3)
321 set_gcr_access(1 << core);
322 else
323 set_gcr_access_cm3(1 << core);
324
325 if (mips_cpc_present()) {
326 /* Reset the core */
327 mips_cpc_lock_other(core);
328
329 if (mips_cm_revision() >= CM_REV_CM3) {
330 /* Run only the requested VP following the reset */
331 write_cpc_co_vp_stop(0xf);
332 write_cpc_co_vp_run(1 << vpe_id);
333
334 /*
335 * Ensure that the VP_RUN register is written before the
336 * core leaves reset.
337 */
338 wmb();
339 }
340
341 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
342
343 timeout = 100;
344 while (true) {
345 stat = read_cpc_co_stat_conf();
346 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
347 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
348
349 /* U6 == coherent execution, ie. the core is up */
350 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
351 break;
352
353 /* Delay a little while before we start warning */
354 if (timeout) {
355 timeout--;
356 mdelay(10);
357 continue;
358 }
359
360 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
361 core, stat);
362 mdelay(1000);
363 }
364
365 mips_cpc_unlock_other();
366 } else {
367 /* Take the core out of reset */
368 write_gcr_co_reset_release(0);
369 }
370
371 mips_cm_unlock_other();
372
373 /* The core is now powered up */
374 bitmap_set(core_power, core, 1);
375 }
376
remote_vpe_boot(void * dummy)377 static void remote_vpe_boot(void *dummy)
378 {
379 unsigned core = cpu_core(¤t_cpu_data);
380 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
381
382 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
383 }
384
cps_boot_secondary(int cpu,struct task_struct * idle)385 static int cps_boot_secondary(int cpu, struct task_struct *idle)
386 {
387 unsigned core = cpu_core(&cpu_data[cpu]);
388 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
389 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
390 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
391 unsigned int remote;
392 int err;
393
394 /* We don't yet support booting CPUs in other clusters */
395 if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
396 return -ENOSYS;
397
398 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
399 vpe_cfg->sp = __KSTK_TOS(idle);
400 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
401
402 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
403
404 preempt_disable();
405
406 if (!test_bit(core, core_power)) {
407 /* Boot a VPE on a powered down core */
408 boot_core(core, vpe_id);
409 goto out;
410 }
411
412 if (cpu_has_vp) {
413 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
414 write_gcr_co_reset_base(core_entry_reg);
415 mips_cm_unlock_other();
416 }
417
418 if (!cpus_are_siblings(cpu, smp_processor_id())) {
419 /* Boot a VPE on another powered up core */
420 for (remote = 0; remote < NR_CPUS; remote++) {
421 if (!cpus_are_siblings(cpu, remote))
422 continue;
423 if (cpu_online(remote))
424 break;
425 }
426 if (remote >= NR_CPUS) {
427 pr_crit("No online CPU in core %u to start CPU%d\n",
428 core, cpu);
429 goto out;
430 }
431
432 err = smp_call_function_single(remote, remote_vpe_boot,
433 NULL, 1);
434 if (err)
435 panic("Failed to call remote CPU\n");
436 goto out;
437 }
438
439 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
440
441 /* Boot a VPE on this core */
442 mips_cps_boot_vpes(core_cfg, vpe_id);
443 out:
444 preempt_enable();
445 return 0;
446 }
447
cps_init_secondary(void)448 static void cps_init_secondary(void)
449 {
450 int core = cpu_core(¤t_cpu_data);
451
452 /* Disable MT - we only want to run 1 TC per VPE */
453 if (cpu_has_mipsmt)
454 dmt();
455
456 if (mips_cm_revision() >= CM_REV_CM3) {
457 unsigned int ident = read_gic_vl_ident();
458
459 /*
460 * Ensure that our calculation of the VP ID matches up with
461 * what the GIC reports, otherwise we'll have configured
462 * interrupts incorrectly.
463 */
464 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
465 }
466
467 if (core > 0 && !read_gcr_cl_coherence())
468 pr_warn("Core %u is not in coherent domain\n", core);
469
470 if (cpu_has_veic)
471 clear_c0_status(ST0_IM);
472 else
473 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
474 STATUSF_IP4 | STATUSF_IP5 |
475 STATUSF_IP6 | STATUSF_IP7);
476 }
477
cps_smp_finish(void)478 static void cps_smp_finish(void)
479 {
480 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
481
482 #ifdef CONFIG_MIPS_MT_FPAFF
483 /* If we have an FPU, enroll ourselves in the FPU-full mask */
484 if (cpu_has_fpu)
485 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
486 #endif /* CONFIG_MIPS_MT_FPAFF */
487
488 local_irq_enable();
489 }
490
491 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
492
493 enum cpu_death {
494 CPU_DEATH_HALT,
495 CPU_DEATH_POWER,
496 };
497
cps_shutdown_this_cpu(enum cpu_death death)498 static void cps_shutdown_this_cpu(enum cpu_death death)
499 {
500 unsigned int cpu, core, vpe_id;
501
502 cpu = smp_processor_id();
503 core = cpu_core(&cpu_data[cpu]);
504
505 if (death == CPU_DEATH_HALT) {
506 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
507
508 pr_debug("Halting core %d VP%d\n", core, vpe_id);
509 if (cpu_has_mipsmt) {
510 /* Halt this TC */
511 write_c0_tchalt(TCHALT_H);
512 instruction_hazard();
513 } else if (cpu_has_vp) {
514 write_cpc_cl_vp_stop(1 << vpe_id);
515
516 /* Ensure that the VP_STOP register is written */
517 wmb();
518 }
519 } else {
520 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
521 pr_debug("Gating power to core %d\n", core);
522 /* Power down the core */
523 cps_pm_enter_state(CPS_PM_POWER_GATED);
524 }
525 }
526 }
527
528 #ifdef CONFIG_KEXEC_CORE
529
cps_kexec_nonboot_cpu(void)530 static void cps_kexec_nonboot_cpu(void)
531 {
532 if (cpu_has_mipsmt || cpu_has_vp)
533 cps_shutdown_this_cpu(CPU_DEATH_HALT);
534 else
535 cps_shutdown_this_cpu(CPU_DEATH_POWER);
536 }
537
538 #endif /* CONFIG_KEXEC_CORE */
539
540 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */
541
542 #ifdef CONFIG_HOTPLUG_CPU
543
cps_cpu_disable(void)544 static int cps_cpu_disable(void)
545 {
546 unsigned cpu = smp_processor_id();
547 struct core_boot_config *core_cfg;
548
549 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
550 return -EINVAL;
551
552 core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
553 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
554 smp_mb__after_atomic();
555 set_cpu_online(cpu, false);
556 calculate_cpu_foreign_map();
557 irq_migrate_all_off_this_cpu();
558
559 return 0;
560 }
561
562 static unsigned cpu_death_sibling;
563 static enum cpu_death cpu_death;
564
play_dead(void)565 void play_dead(void)
566 {
567 unsigned int cpu;
568
569 local_irq_disable();
570 idle_task_exit();
571 cpu = smp_processor_id();
572 cpu_death = CPU_DEATH_POWER;
573
574 pr_debug("CPU%d going offline\n", cpu);
575
576 if (cpu_has_mipsmt || cpu_has_vp) {
577 /* Look for another online VPE within the core */
578 for_each_online_cpu(cpu_death_sibling) {
579 if (!cpus_are_siblings(cpu, cpu_death_sibling))
580 continue;
581
582 /*
583 * There is an online VPE within the core. Just halt
584 * this TC and leave the core alone.
585 */
586 cpu_death = CPU_DEATH_HALT;
587 break;
588 }
589 }
590
591 cpuhp_ap_report_dead();
592
593 cps_shutdown_this_cpu(cpu_death);
594
595 /* This should never be reached */
596 panic("Failed to offline CPU %u", cpu);
597 }
598
wait_for_sibling_halt(void * ptr_cpu)599 static void wait_for_sibling_halt(void *ptr_cpu)
600 {
601 unsigned cpu = (unsigned long)ptr_cpu;
602 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
603 unsigned halted;
604 unsigned long flags;
605
606 do {
607 local_irq_save(flags);
608 settc(vpe_id);
609 halted = read_tc_c0_tchalt();
610 local_irq_restore(flags);
611 } while (!(halted & TCHALT_H));
612 }
613
cps_cpu_die(unsigned int cpu)614 static void cps_cpu_die(unsigned int cpu) { }
615
cps_cleanup_dead_cpu(unsigned cpu)616 static void cps_cleanup_dead_cpu(unsigned cpu)
617 {
618 unsigned core = cpu_core(&cpu_data[cpu]);
619 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
620 ktime_t fail_time;
621 unsigned stat;
622 int err;
623
624 /*
625 * Now wait for the CPU to actually offline. Without doing this that
626 * offlining may race with one or more of:
627 *
628 * - Onlining the CPU again.
629 * - Powering down the core if another VPE within it is offlined.
630 * - A sibling VPE entering a non-coherent state.
631 *
632 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
633 * with which we could race, so do nothing.
634 */
635 if (cpu_death == CPU_DEATH_POWER) {
636 /*
637 * Wait for the core to enter a powered down or clock gated
638 * state, the latter happening when a JTAG probe is connected
639 * in which case the CPC will refuse to power down the core.
640 */
641 fail_time = ktime_add_ms(ktime_get(), 2000);
642 do {
643 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
644 mips_cpc_lock_other(core);
645 stat = read_cpc_co_stat_conf();
646 stat &= CPC_Cx_STAT_CONF_SEQSTATE;
647 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
648 mips_cpc_unlock_other();
649 mips_cm_unlock_other();
650
651 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
652 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
653 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
654 break;
655
656 /*
657 * The core ought to have powered down, but didn't &
658 * now we don't really know what state it's in. It's
659 * likely that its _pwr_up pin has been wired to logic
660 * 1 & it powered back up as soon as we powered it
661 * down...
662 *
663 * The best we can do is warn the user & continue in
664 * the hope that the core is doing nothing harmful &
665 * might behave properly if we online it later.
666 */
667 if (WARN(ktime_after(ktime_get(), fail_time),
668 "CPU%u hasn't powered down, seq. state %u\n",
669 cpu, stat))
670 break;
671 } while (1);
672
673 /* Indicate the core is powered off */
674 bitmap_clear(core_power, core, 1);
675 } else if (cpu_has_mipsmt) {
676 /*
677 * Have a CPU with access to the offlined CPUs registers wait
678 * for its TC to halt.
679 */
680 err = smp_call_function_single(cpu_death_sibling,
681 wait_for_sibling_halt,
682 (void *)(unsigned long)cpu, 1);
683 if (err)
684 panic("Failed to call remote sibling CPU\n");
685 } else if (cpu_has_vp) {
686 do {
687 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
688 stat = read_cpc_co_vp_running();
689 mips_cm_unlock_other();
690 } while (stat & (1 << vpe_id));
691 }
692 }
693
694 #endif /* CONFIG_HOTPLUG_CPU */
695
696 static const struct plat_smp_ops cps_smp_ops = {
697 .smp_setup = cps_smp_setup,
698 .prepare_cpus = cps_prepare_cpus,
699 .boot_secondary = cps_boot_secondary,
700 .init_secondary = cps_init_secondary,
701 .smp_finish = cps_smp_finish,
702 .send_ipi_single = mips_smp_send_ipi_single,
703 .send_ipi_mask = mips_smp_send_ipi_mask,
704 #ifdef CONFIG_HOTPLUG_CPU
705 .cpu_disable = cps_cpu_disable,
706 .cpu_die = cps_cpu_die,
707 .cleanup_dead_cpu = cps_cleanup_dead_cpu,
708 #endif
709 #ifdef CONFIG_KEXEC_CORE
710 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu,
711 #endif
712 };
713
mips_cps_smp_in_use(void)714 bool mips_cps_smp_in_use(void)
715 {
716 extern const struct plat_smp_ops *mp_ops;
717 return mp_ops == &cps_smp_ops;
718 }
719
register_cps_smp_ops(void)720 int register_cps_smp_ops(void)
721 {
722 if (!mips_cm_present()) {
723 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
724 return -ENODEV;
725 }
726
727 /* check we have a GIC - we need one for IPIs */
728 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
729 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
730 return -ENODEV;
731 }
732
733 register_smp_ops(&cps_smp_ops);
734 return 0;
735 }
736