1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 aliases { }; 28 29 chosen { }; 30 31 cpus { 32 #address-cells = <2>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "qcom,kryo360"; 38 reg = <0x0 0x0>; 39 enable-method = "psci"; 40 capacity-dmips-mhz = <610>; 41 dynamic-power-coefficient = <203>; 42 qcom,freq-domain = <&cpufreq_hw 0>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 45 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 46 power-domains = <&CPU_PD0>; 47 power-domain-names = "psci"; 48 next-level-cache = <&L2_0>; 49 L2_0: l2-cache { 50 compatible = "cache"; 51 next-level-cache = <&L3_0>; 52 cache-level = <2>; 53 cache-unified; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 cache-level = <3>; 57 cache-unified; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo360"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <610>; 68 dynamic-power-coefficient = <203>; 69 qcom,freq-domain = <&cpufreq_hw 0>; 70 operating-points-v2 = <&cpu0_opp_table>; 71 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 72 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 73 power-domains = <&CPU_PD1>; 74 power-domain-names = "psci"; 75 next-level-cache = <&L2_100>; 76 L2_100: l2-cache { 77 compatible = "cache"; 78 cache-level = <2>; 79 cache-unified; 80 next-level-cache = <&L3_0>; 81 }; 82 }; 83 84 CPU2: cpu@200 { 85 device_type = "cpu"; 86 compatible = "qcom,kryo360"; 87 reg = <0x0 0x200>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <610>; 90 dynamic-power-coefficient = <203>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 94 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95 power-domains = <&CPU_PD2>; 96 power-domain-names = "psci"; 97 next-level-cache = <&L2_200>; 98 L2_200: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&L3_0>; 103 }; 104 }; 105 106 CPU3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo360"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 capacity-dmips-mhz = <610>; 112 dynamic-power-coefficient = <203>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 operating-points-v2 = <&cpu0_opp_table>; 115 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 116 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 117 power-domains = <&CPU_PD3>; 118 power-domain-names = "psci"; 119 next-level-cache = <&L2_300>; 120 L2_300: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU4: cpu@400 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo360"; 131 reg = <0x0 0x400>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <610>; 134 dynamic-power-coefficient = <203>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 power-domains = <&CPU_PD4>; 140 power-domain-names = "psci"; 141 next-level-cache = <&L2_400>; 142 L2_400: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU5: cpu@500 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo360"; 153 reg = <0x0 0x500>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <610>; 156 dynamic-power-coefficient = <203>; 157 qcom,freq-domain = <&cpufreq_hw 0>; 158 operating-points-v2 = <&cpu0_opp_table>; 159 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 next-level-cache = <&L2_500>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo360"; 175 reg = <0x0 0x600>; 176 enable-method = "psci"; 177 capacity-dmips-mhz = <1024>; 178 dynamic-power-coefficient = <393>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu6_opp_table>; 181 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 182 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 183 power-domains = <&CPU_PD6>; 184 power-domain-names = "psci"; 185 next-level-cache = <&L2_600>; 186 L2_600: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo360"; 197 reg = <0x0 0x700>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 dynamic-power-coefficient = <393>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu6_opp_table>; 203 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD7>; 206 power-domain-names = "psci"; 207 next-level-cache = <&L2_700>; 208 L2_700: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 cache-unified; 212 next-level-cache = <&L3_0>; 213 }; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&CPU0>; 220 }; 221 222 core1 { 223 cpu = <&CPU1>; 224 }; 225 226 core2 { 227 cpu = <&CPU2>; 228 }; 229 230 core3 { 231 cpu = <&CPU3>; 232 }; 233 234 core4 { 235 cpu = <&CPU4>; 236 }; 237 238 core5 { 239 cpu = <&CPU5>; 240 }; 241 242 core6 { 243 cpu = <&CPU6>; 244 }; 245 246 core7 { 247 cpu = <&CPU7>; 248 }; 249 }; 250 }; 251 252 idle-states { 253 entry-method = "psci"; 254 255 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "little-rail-power-collapse"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <702>; 260 exit-latency-us = <915>; 261 min-residency-us = <1617>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "big-rail-power-collapse"; 268 arm,psci-suspend-param = <0x40000004>; 269 entry-latency-us = <526>; 270 exit-latency-us = <1854>; 271 min-residency-us = <2380>; 272 local-timer-stop; 273 }; 274 }; 275 276 domain-idle-states { 277 CLUSTER_SLEEP_0: cluster-sleep-0 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x4100c244>; 280 entry-latency-us = <3263>; 281 exit-latency-us = <6562>; 282 min-residency-us = <9825>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm { 289 compatible = "qcom,scm-sdm670", "qcom,scm"; 290 }; 291 }; 292 293 memory@80000000 { 294 device_type = "memory"; 295 /* We expect the bootloader to fill in the size */ 296 reg = <0x0 0x80000000 0x0 0x0>; 297 }; 298 299 cpu0_opp_table: opp-table-cpu0 { 300 compatible = "operating-points-v2"; 301 opp-shared; 302 303 cpu0_opp1: opp-300000000 { 304 opp-hz = /bits/ 64 <300000000>; 305 opp-peak-kBps = <400000 4800000>; 306 }; 307 308 cpu0_opp2: opp-576000000 { 309 opp-hz = /bits/ 64 <576000000>; 310 opp-peak-kBps = <400000 4800000>; 311 }; 312 313 cpu0_opp3: opp-748800000 { 314 opp-hz = /bits/ 64 <748800000>; 315 opp-peak-kBps = <1200000 4800000>; 316 }; 317 318 cpu0_opp4: opp-998400000 { 319 opp-hz = /bits/ 64 <998400000>; 320 opp-peak-kBps = <1804000 8908800>; 321 }; 322 323 cpu0_opp5: opp-1209600000 { 324 opp-hz = /bits/ 64 <1209600000>; 325 opp-peak-kBps = <2188000 8908800>; 326 }; 327 328 cpu0_opp6: opp-1324800000 { 329 opp-hz = /bits/ 64 <1324800000>; 330 opp-peak-kBps = <2188000 13516800>; 331 }; 332 333 cpu0_opp7: opp-1516800000 { 334 opp-hz = /bits/ 64 <1516800000>; 335 opp-peak-kBps = <3072000 15052800>; 336 }; 337 338 cpu0_opp8: opp-1612800000 { 339 opp-hz = /bits/ 64 <1612800000>; 340 opp-peak-kBps = <3072000 22118400>; 341 }; 342 343 cpu0_opp9: opp-1708800000 { 344 opp-hz = /bits/ 64 <1708800000>; 345 opp-peak-kBps = <4068000 23040000>; 346 }; 347 }; 348 349 cpu6_opp_table: opp-table-cpu6 { 350 compatible = "operating-points-v2"; 351 opp-shared; 352 353 cpu6_opp1: opp-300000000 { 354 opp-hz = /bits/ 64 <300000000>; 355 opp-peak-kBps = <400000 4800000>; 356 }; 357 358 cpu6_opp2: opp-652800000 { 359 opp-hz = /bits/ 64 <652800000>; 360 opp-peak-kBps = <400000 4800000>; 361 }; 362 363 cpu6_opp3: opp-825600000 { 364 opp-hz = /bits/ 64 <825600000>; 365 opp-peak-kBps = <1200000 4800000>; 366 }; 367 368 cpu6_opp4: opp-979200000 { 369 opp-hz = /bits/ 64 <979200000>; 370 opp-peak-kBps = <1200000 4800000>; 371 }; 372 373 cpu6_opp5: opp-1132800000 { 374 opp-hz = /bits/ 64 <1132800000>; 375 opp-peak-kBps = <2188000 8908800>; 376 }; 377 378 cpu6_opp6: opp-1363200000 { 379 opp-hz = /bits/ 64 <1363200000>; 380 opp-peak-kBps = <4068000 12902400>; 381 }; 382 383 cpu6_opp7: opp-1536000000 { 384 opp-hz = /bits/ 64 <1536000000>; 385 opp-peak-kBps = <4068000 12902400>; 386 }; 387 388 cpu6_opp8: opp-1747200000 { 389 opp-hz = /bits/ 64 <1747200000>; 390 opp-peak-kBps = <4068000 15052800>; 391 }; 392 393 cpu6_opp9: opp-1843200000 { 394 opp-hz = /bits/ 64 <1843200000>; 395 opp-peak-kBps = <4068000 15052800>; 396 }; 397 398 cpu6_opp10: opp-1996800000 { 399 opp-hz = /bits/ 64 <1996800000>; 400 opp-peak-kBps = <6220000 19046400>; 401 }; 402 }; 403 404 dsi_opp_table: opp-table-dsi { 405 compatible = "operating-points-v2"; 406 407 opp-19200000 { 408 opp-hz = /bits/ 64 <19200000>; 409 required-opps = <&rpmhpd_opp_min_svs>; 410 }; 411 412 opp-180000000 { 413 opp-hz = /bits/ 64 <180000000>; 414 required-opps = <&rpmhpd_opp_low_svs>; 415 }; 416 417 opp-275000000 { 418 opp-hz = /bits/ 64 <275000000>; 419 required-opps = <&rpmhpd_opp_svs>; 420 }; 421 422 opp-358000000 { 423 opp-hz = /bits/ 64 <358000000>; 424 required-opps = <&rpmhpd_opp_svs_l1>; 425 }; 426 }; 427 428 psci { 429 compatible = "arm,psci-1.0"; 430 method = "smc"; 431 432 CPU_PD0: power-domain-cpu0 { 433 #power-domain-cells = <0>; 434 power-domains = <&CLUSTER_PD>; 435 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 436 }; 437 438 CPU_PD1: power-domain-cpu1 { 439 #power-domain-cells = <0>; 440 power-domains = <&CLUSTER_PD>; 441 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 442 }; 443 444 CPU_PD2: power-domain-cpu2 { 445 #power-domain-cells = <0>; 446 power-domains = <&CLUSTER_PD>; 447 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 448 }; 449 450 CPU_PD3: power-domain-cpu3 { 451 #power-domain-cells = <0>; 452 power-domains = <&CLUSTER_PD>; 453 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 454 }; 455 456 CPU_PD4: power-domain-cpu4 { 457 #power-domain-cells = <0>; 458 power-domains = <&CLUSTER_PD>; 459 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 460 }; 461 462 CPU_PD5: power-domain-cpu5 { 463 #power-domain-cells = <0>; 464 power-domains = <&CLUSTER_PD>; 465 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 466 }; 467 468 CPU_PD6: power-domain-cpu6 { 469 #power-domain-cells = <0>; 470 power-domains = <&CLUSTER_PD>; 471 domain-idle-states = <&BIG_CPU_SLEEP_0>; 472 }; 473 474 CPU_PD7: power-domain-cpu7 { 475 #power-domain-cells = <0>; 476 power-domains = <&CLUSTER_PD>; 477 domain-idle-states = <&BIG_CPU_SLEEP_0>; 478 }; 479 480 CLUSTER_PD: power-domain-cluster { 481 #power-domain-cells = <0>; 482 domain-idle-states = <&CLUSTER_SLEEP_0>; 483 }; 484 }; 485 486 reserved-memory { 487 #address-cells = <2>; 488 #size-cells = <2>; 489 ranges; 490 491 hyp_mem: hyp-mem@85700000 { 492 reg = <0 0x85700000 0 0x600000>; 493 no-map; 494 }; 495 496 xbl_mem: xbl-mem@85e00000 { 497 reg = <0 0x85e00000 0 0x100000>; 498 no-map; 499 }; 500 501 aop_mem: aop-mem@85fc0000 { 502 reg = <0 0x85fc0000 0 0x20000>; 503 no-map; 504 }; 505 506 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 507 compatible = "qcom,cmd-db"; 508 reg = <0 0x85fe0000 0 0x20000>; 509 no-map; 510 }; 511 512 smem@86000000 { 513 compatible = "qcom,smem"; 514 reg = <0 0x86000000 0 0x200000>; 515 no-map; 516 hwlocks = <&tcsr_mutex 3>; 517 }; 518 519 tz_mem: tz@86200000 { 520 reg = <0 0x86200000 0 0x2d00000>; 521 no-map; 522 }; 523 524 camera_mem: camera-mem@8ab00000 { 525 reg = <0 0x8ab00000 0 0x500000>; 526 no-map; 527 }; 528 529 mpss_region: mpss@8b000000 { 530 reg = <0 0x8b000000 0 0x7e00000>; 531 no-map; 532 }; 533 534 venus_mem: venus@92e00000 { 535 reg = <0 0x92e00000 0 0x500000>; 536 no-map; 537 }; 538 539 wlan_msa_mem: wlan-msa@93300000 { 540 reg = <0 0x93300000 0 0x100000>; 541 no-map; 542 }; 543 544 cdsp_mem: cdsp@93400000 { 545 reg = <0 0x93400000 0 0x800000>; 546 no-map; 547 }; 548 549 mba_region: mba@93c00000 { 550 reg = <0 0x93c00000 0 0x200000>; 551 no-map; 552 }; 553 554 adsp_mem: adsp@93e00000 { 555 reg = <0 0x93e00000 0 0x1e00000>; 556 no-map; 557 }; 558 559 ipa_fw_mem: ipa-fw@95c00000 { 560 reg = <0 0x95c00000 0 0x10000>; 561 no-map; 562 }; 563 564 ipa_gsi_mem: ipa-gsi@95c10000 { 565 reg = <0 0x95c10000 0 0x5000>; 566 no-map; 567 }; 568 569 gpu_mem: gpu@95c15000 { 570 reg = <0 0x95c15000 0 0x2000>; 571 no-map; 572 }; 573 574 spss_mem: spss@97b00000 { 575 reg = <0 0x97b00000 0 0x100000>; 576 no-map; 577 }; 578 579 qseecom_mem: qseecom@9e400000 { 580 reg = <0 0x9e400000 0 0x1400000>; 581 no-map; 582 }; 583 }; 584 585 timer { 586 compatible = "arm,armv8-timer"; 587 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 588 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 589 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 590 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 591 }; 592 593 soc: soc@0 { 594 #address-cells = <2>; 595 #size-cells = <2>; 596 ranges = <0 0 0 0 0x10 0>; 597 dma-ranges = <0 0 0 0 0x10 0>; 598 compatible = "simple-bus"; 599 600 gcc: clock-controller@100000 { 601 compatible = "qcom,gcc-sdm670"; 602 reg = <0 0x00100000 0 0x1f0000>; 603 clocks = <&rpmhcc RPMH_CXO_CLK>, 604 <&rpmhcc RPMH_CXO_CLK_A>, 605 <&sleep_clk>; 606 clock-names = "bi_tcxo", 607 "bi_tcxo_ao", 608 "sleep_clk"; 609 #clock-cells = <1>; 610 #reset-cells = <1>; 611 #power-domain-cells = <1>; 612 }; 613 614 qfprom: qfprom@784000 { 615 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 616 reg = <0 0x00784000 0 0x1000>; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 620 qusb2_hstx_trim: hstx-trim@1eb { 621 reg = <0x1eb 0x1>; 622 bits = <1 4>; 623 }; 624 }; 625 626 sdhc_1: mmc@7c4000 { 627 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 628 reg = <0 0x007c4000 0 0x1000>, 629 <0 0x007c5000 0 0x1000>, 630 <0 0x007c8000 0 0x8000>; 631 reg-names = "hc", "cqhci", "ice"; 632 633 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 635 interrupt-names = "hc_irq", "pwr_irq"; 636 637 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 638 <&gcc GCC_SDCC1_APPS_CLK>, 639 <&rpmhcc RPMH_CXO_CLK>, 640 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 641 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 642 clock-names = "iface", "core", "xo", "ice", "bus"; 643 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, 644 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; 645 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 646 operating-points-v2 = <&sdhc1_opp_table>; 647 648 iommus = <&apps_smmu 0x140 0xf>; 649 650 pinctrl-names = "default", "sleep"; 651 pinctrl-0 = <&sdc1_state_on>; 652 pinctrl-1 = <&sdc1_state_off>; 653 power-domains = <&rpmhpd SDM670_CX>; 654 655 bus-width = <8>; 656 non-removable; 657 658 status = "disabled"; 659 660 sdhc1_opp_table: opp-table { 661 compatible = "operating-points-v2"; 662 663 opp-20000000 { 664 opp-hz = /bits/ 64 <20000000>; 665 required-opps = <&rpmhpd_opp_min_svs>; 666 opp-peak-kBps = <80000 80000>; 667 opp-avg-kBps = <52286 80000>; 668 }; 669 670 opp-50000000 { 671 opp-hz = /bits/ 64 <50000000>; 672 required-opps = <&rpmhpd_opp_low_svs>; 673 opp-peak-kBps = <200000 100000>; 674 opp-avg-kBps = <130718 100000>; 675 }; 676 677 opp-100000000 { 678 opp-hz = /bits/ 64 <100000000>; 679 required-opps = <&rpmhpd_opp_svs>; 680 opp-peak-kBps = <200000 130000>; 681 opp-avg-kBps = <130718 130000>; 682 }; 683 684 opp-384000000 { 685 opp-hz = /bits/ 64 <384000000>; 686 required-opps = <&rpmhpd_opp_nom>; 687 opp-peak-kBps = <4096000 4096000>; 688 opp-avg-kBps = <1338562 1338562>; 689 }; 690 }; 691 }; 692 693 gpi_dma0: dma-controller@800000 { 694 #dma-cells = <3>; 695 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 696 reg = <0 0x00800000 0 0x60000>; 697 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 710 dma-channels = <13>; 711 dma-channel-mask = <0xfa>; 712 iommus = <&apps_smmu 0x16 0x0>; 713 status = "disabled"; 714 }; 715 716 qupv3_id_0: geniqup@8c0000 { 717 compatible = "qcom,geni-se-qup"; 718 reg = <0 0x008c0000 0 0x6000>; 719 clock-names = "m-ahb", "s-ahb"; 720 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 721 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 722 iommus = <&apps_smmu 0x3 0x0>; 723 #address-cells = <2>; 724 #size-cells = <2>; 725 ranges; 726 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; 727 interconnect-names = "qup-core"; 728 status = "disabled"; 729 730 i2c0: i2c@880000 { 731 compatible = "qcom,geni-i2c"; 732 reg = <0 0x00880000 0 0x4000>; 733 clock-names = "se"; 734 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&qup_i2c0_default>; 737 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 power-domains = <&rpmhpd SDM670_CX>; 741 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 742 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 743 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 744 interconnect-names = "qup-core", "qup-config", "qup-memory"; 745 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 746 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 747 dma-names = "tx", "rx"; 748 status = "disabled"; 749 }; 750 751 i2c1: i2c@884000 { 752 compatible = "qcom,geni-i2c"; 753 reg = <0 0x00884000 0 0x4000>; 754 clock-names = "se"; 755 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&qup_i2c1_default>; 758 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 power-domains = <&rpmhpd SDM670_CX>; 762 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 763 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 764 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 765 interconnect-names = "qup-core", "qup-config", "qup-memory"; 766 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 767 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 768 dma-names = "tx", "rx"; 769 status = "disabled"; 770 }; 771 772 i2c2: i2c@888000 { 773 compatible = "qcom,geni-i2c"; 774 reg = <0 0x00888000 0 0x4000>; 775 clock-names = "se"; 776 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 777 pinctrl-names = "default"; 778 pinctrl-0 = <&qup_i2c2_default>; 779 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 power-domains = <&rpmhpd SDM670_CX>; 783 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 784 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 785 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 786 interconnect-names = "qup-core", "qup-config", "qup-memory"; 787 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 788 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 789 dma-names = "tx", "rx"; 790 status = "disabled"; 791 }; 792 793 i2c3: i2c@88c000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x0088c000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c3_default>; 800 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 power-domains = <&rpmhpd SDM670_CX>; 804 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 805 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 806 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 807 interconnect-names = "qup-core", "qup-config", "qup-memory"; 808 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 809 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 810 dma-names = "tx", "rx"; 811 status = "disabled"; 812 }; 813 814 i2c4: i2c@890000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x00890000 0 0x4000>; 817 clock-names = "se"; 818 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&qup_i2c4_default>; 821 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 power-domains = <&rpmhpd SDM670_CX>; 825 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 826 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 827 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 828 interconnect-names = "qup-core", "qup-config", "qup-memory"; 829 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 830 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 831 dma-names = "tx", "rx"; 832 status = "disabled"; 833 }; 834 835 i2c5: i2c@894000 { 836 compatible = "qcom,geni-i2c"; 837 reg = <0 0x00894000 0 0x4000>; 838 clock-names = "se"; 839 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 840 pinctrl-names = "default"; 841 pinctrl-0 = <&qup_i2c5_default>; 842 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 power-domains = <&rpmhpd SDM670_CX>; 846 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 847 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 848 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 849 interconnect-names = "qup-core", "qup-config", "qup-memory"; 850 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 851 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 status = "disabled"; 854 }; 855 856 i2c6: i2c@898000 { 857 compatible = "qcom,geni-i2c"; 858 reg = <0 0x00898000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_i2c6_default>; 863 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 power-domains = <&rpmhpd SDM670_CX>; 867 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 868 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 869 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 870 interconnect-names = "qup-core", "qup-config", "qup-memory"; 871 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 872 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 873 dma-names = "tx", "rx"; 874 status = "disabled"; 875 }; 876 877 i2c7: i2c@89c000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0 0x0089c000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_i2c7_default>; 884 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 power-domains = <&rpmhpd SDM670_CX>; 888 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 889 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 890 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 892 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 893 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 894 dma-names = "tx", "rx"; 895 status = "disabled"; 896 }; 897 }; 898 899 gpi_dma1: dma-controller@a00000 { 900 #dma-cells = <3>; 901 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 902 reg = <0 0x00a00000 0 0x60000>; 903 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 916 dma-channels = <13>; 917 dma-channel-mask = <0xfa>; 918 iommus = <&apps_smmu 0x6d6 0x0>; 919 status = "disabled"; 920 }; 921 922 qupv3_id_1: geniqup@ac0000 { 923 compatible = "qcom,geni-se-qup"; 924 reg = <0 0x00ac0000 0 0x6000>; 925 clock-names = "m-ahb", "s-ahb"; 926 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 927 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 928 iommus = <&apps_smmu 0x6c3 0x0>; 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges; 932 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; 933 interconnect-names = "qup-core"; 934 status = "disabled"; 935 936 i2c8: i2c@a80000 { 937 compatible = "qcom,geni-i2c"; 938 reg = <0 0x00a80000 0 0x4000>; 939 clock-names = "se"; 940 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&qup_i2c8_default>; 943 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 power-domains = <&rpmhpd SDM670_CX>; 947 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 948 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 949 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 950 interconnect-names = "qup-core", "qup-config", "qup-memory"; 951 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 952 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 status = "disabled"; 955 }; 956 957 i2c9: i2c@a84000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0 0x00a84000 0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_i2c9_default>; 964 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 power-domains = <&rpmhpd SDM670_CX>; 968 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 969 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 970 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 973 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 i2c10: i2c@a88000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00a88000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_i2c10_default>; 985 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 power-domains = <&rpmhpd SDM670_CX>; 989 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 990 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 991 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 992 interconnect-names = "qup-core", "qup-config", "qup-memory"; 993 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 994 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 status = "disabled"; 997 }; 998 999 i2c11: i2c@a8c000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00a8c000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c11_default>; 1006 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 power-domains = <&rpmhpd SDM670_CX>; 1010 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1011 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1012 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1015 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1016 dma-names = "tx", "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c12: i2c@a90000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00a90000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c12_default>; 1027 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 power-domains = <&rpmhpd SDM670_CX>; 1031 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1032 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1033 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1034 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1035 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1036 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1037 dma-names = "tx", "rx"; 1038 status = "disabled"; 1039 }; 1040 1041 i2c13: i2c@a94000 { 1042 compatible = "qcom,geni-i2c"; 1043 reg = <0 0x00a94000 0 0x4000>; 1044 clock-names = "se"; 1045 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_i2c13_default>; 1048 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 power-domains = <&rpmhpd SDM670_CX>; 1052 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1053 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1054 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1055 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1056 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1057 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 status = "disabled"; 1060 }; 1061 1062 i2c14: i2c@a98000 { 1063 compatible = "qcom,geni-i2c"; 1064 reg = <0 0x00a98000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c14_default>; 1069 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 power-domains = <&rpmhpd SDM670_CX>; 1073 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1074 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1075 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1078 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 status = "disabled"; 1081 }; 1082 1083 i2c15: i2c@a9c000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0 0x00a9c000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_i2c15_default>; 1090 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 power-domains = <&rpmhpd SDM670_CX>; 1094 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1095 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1096 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1097 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1098 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1099 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 status = "disabled"; 1102 }; 1103 }; 1104 1105 mem_noc: interconnect@1380000 { 1106 compatible = "qcom,sdm670-mem-noc"; 1107 reg = <0 0x01380000 0 0x27200>; 1108 #interconnect-cells = <2>; 1109 qcom,bcm-voters = <&apps_bcm_voter>; 1110 }; 1111 1112 dc_noc: interconnect@14e0000 { 1113 compatible = "qcom,sdm670-dc-noc"; 1114 reg = <0 0x014e0000 0 0x400>; 1115 #interconnect-cells = <2>; 1116 qcom,bcm-voters = <&apps_bcm_voter>; 1117 }; 1118 1119 config_noc: interconnect@1500000 { 1120 compatible = "qcom,sdm670-config-noc"; 1121 reg = <0 0x01500000 0 0x5080>; 1122 #interconnect-cells = <2>; 1123 qcom,bcm-voters = <&apps_bcm_voter>; 1124 }; 1125 1126 system_noc: interconnect@1620000 { 1127 compatible = "qcom,sdm670-system-noc"; 1128 reg = <0 0x01620000 0 0x18080>; 1129 #interconnect-cells = <2>; 1130 qcom,bcm-voters = <&apps_bcm_voter>; 1131 }; 1132 1133 aggre1_noc: interconnect@16e0000 { 1134 compatible = "qcom,sdm670-aggre1-noc"; 1135 reg = <0 0x016e0000 0 0x15080>; 1136 #interconnect-cells = <2>; 1137 qcom,bcm-voters = <&apps_bcm_voter>; 1138 }; 1139 1140 aggre2_noc: interconnect@1700000 { 1141 compatible = "qcom,sdm670-aggre2-noc"; 1142 reg = <0 0x01700000 0 0x1f300>; 1143 #interconnect-cells = <2>; 1144 qcom,bcm-voters = <&apps_bcm_voter>; 1145 }; 1146 1147 mmss_noc: interconnect@1740000 { 1148 compatible = "qcom,sdm670-mmss-noc"; 1149 reg = <0 0x01740000 0 0x1c100>; 1150 #interconnect-cells = <2>; 1151 qcom,bcm-voters = <&apps_bcm_voter>; 1152 }; 1153 1154 tcsr_mutex: hwlock@1f40000 { 1155 compatible = "qcom,tcsr-mutex"; 1156 reg = <0 0x01f40000 0 0x20000>; 1157 #hwlock-cells = <1>; 1158 }; 1159 1160 tlmm: pinctrl@3400000 { 1161 compatible = "qcom,sdm670-tlmm"; 1162 reg = <0 0x03400000 0 0xc00000>; 1163 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1164 gpio-controller; 1165 #gpio-cells = <2>; 1166 interrupt-controller; 1167 #interrupt-cells = <2>; 1168 gpio-ranges = <&tlmm 0 0 151>; 1169 wakeup-parent = <&pdc>; 1170 1171 qup_i2c0_default: qup-i2c0-default-state { 1172 pins = "gpio0", "gpio1"; 1173 function = "qup0"; 1174 }; 1175 1176 qup_i2c1_default: qup-i2c1-default-state { 1177 pins = "gpio17", "gpio18"; 1178 function = "qup1"; 1179 }; 1180 1181 qup_i2c2_default: qup-i2c2-default-state { 1182 pins = "gpio27", "gpio28"; 1183 function = "qup2"; 1184 }; 1185 1186 qup_i2c3_default: qup-i2c3-default-state { 1187 pins = "gpio41", "gpio42"; 1188 function = "qup3"; 1189 }; 1190 1191 qup_i2c4_default: qup-i2c4-default-state { 1192 pins = "gpio89", "gpio90"; 1193 function = "qup4"; 1194 }; 1195 1196 qup_i2c5_default: qup-i2c5-default-state { 1197 pins = "gpio85", "gpio86"; 1198 function = "qup5"; 1199 }; 1200 1201 qup_i2c6_default: qup-i2c6-default-state { 1202 pins = "gpio45", "gpio46"; 1203 function = "qup6"; 1204 }; 1205 1206 qup_i2c7_default: qup-i2c7-default-state { 1207 pins = "gpio93", "gpio94"; 1208 function = "qup7"; 1209 }; 1210 1211 qup_i2c8_default: qup-i2c8-default-state { 1212 pins = "gpio65", "gpio66"; 1213 function = "qup8"; 1214 }; 1215 1216 qup_i2c9_default: qup-i2c9-default-state { 1217 pins = "gpio6", "gpio7"; 1218 function = "qup9"; 1219 }; 1220 1221 qup_i2c10_default: qup-i2c10-default-state { 1222 pins = "gpio55", "gpio56"; 1223 function = "qup10"; 1224 }; 1225 1226 qup_i2c11_default: qup-i2c11-default-state { 1227 pins = "gpio31", "gpio32"; 1228 function = "qup11"; 1229 }; 1230 1231 qup_i2c12_default: qup-i2c12-default-state { 1232 pins = "gpio49", "gpio50"; 1233 function = "qup12"; 1234 }; 1235 1236 qup_i2c13_default: qup-i2c13-default-state { 1237 pins = "gpio105", "gpio106"; 1238 function = "qup13"; 1239 }; 1240 1241 qup_i2c14_default: qup-i2c14-default-state { 1242 pins = "gpio33", "gpio34"; 1243 function = "qup14"; 1244 }; 1245 1246 qup_i2c15_default: qup-i2c15-default-state { 1247 pins = "gpio81", "gpio82"; 1248 function = "qup15"; 1249 }; 1250 1251 sdc1_state_on: sdc1-on-state { 1252 clk-pins { 1253 pins = "sdc1_clk"; 1254 bias-disable; 1255 drive-strength = <16>; 1256 }; 1257 1258 cmd-pins { 1259 pins = "sdc1_cmd"; 1260 bias-pull-up; 1261 drive-strength = <10>; 1262 }; 1263 1264 data-pins { 1265 pins = "sdc1_data"; 1266 bias-pull-up; 1267 drive-strength = <10>; 1268 }; 1269 1270 rclk-pins { 1271 pins = "sdc1_rclk"; 1272 bias-pull-down; 1273 }; 1274 }; 1275 1276 sdc1_state_off: sdc1-off-state { 1277 clk-pins { 1278 pins = "sdc1_clk"; 1279 bias-disable; 1280 drive-strength = <2>; 1281 }; 1282 1283 cmd-pins { 1284 pins = "sdc1_cmd"; 1285 bias-pull-up; 1286 drive-strength = <2>; 1287 }; 1288 1289 data-pins { 1290 pins = "sdc1_data"; 1291 bias-pull-up; 1292 drive-strength = <2>; 1293 }; 1294 1295 rclk-pins { 1296 pins = "sdc1_rclk"; 1297 bias-pull-down; 1298 }; 1299 }; 1300 }; 1301 1302 usb_1_hsphy: phy@88e2000 { 1303 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 1304 reg = <0 0x088e2000 0 0x400>; 1305 #phy-cells = <0>; 1306 1307 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1308 <&rpmhcc RPMH_CXO_CLK>; 1309 clock-names = "cfg_ahb", "ref"; 1310 1311 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1312 1313 nvmem-cells = <&qusb2_hstx_trim>; 1314 1315 status = "disabled"; 1316 }; 1317 1318 usb_1: usb@a6f8800 { 1319 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 1320 reg = <0 0x0a6f8800 0 0x400>; 1321 #address-cells = <2>; 1322 #size-cells = <2>; 1323 ranges; 1324 dma-ranges; 1325 1326 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1327 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1328 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1329 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1330 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1331 clock-names = "cfg_noc", 1332 "core", 1333 "iface", 1334 "sleep", 1335 "mock_utmi"; 1336 1337 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1338 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1339 assigned-clock-rates = <19200000>, <150000000>; 1340 1341 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1342 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1343 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 1344 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1345 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 1346 interrupt-names = "pwr_event", 1347 "hs_phy_irq", 1348 "dp_hs_phy_irq", 1349 "dm_hs_phy_irq", 1350 "ss_phy_irq"; 1351 1352 power-domains = <&gcc USB30_PRIM_GDSC>; 1353 1354 resets = <&gcc GCC_USB30_PRIM_BCR>; 1355 1356 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, 1357 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1358 interconnect-names = "usb-ddr", "apps-usb"; 1359 1360 status = "disabled"; 1361 1362 usb_1_dwc3: usb@a600000 { 1363 compatible = "snps,dwc3"; 1364 reg = <0 0x0a600000 0 0xcd00>; 1365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1366 iommus = <&apps_smmu 0x740 0>; 1367 snps,dis_u2_susphy_quirk; 1368 snps,dis_enblslpm_quirk; 1369 phys = <&usb_1_hsphy>; 1370 phy-names = "usb2-phy"; 1371 }; 1372 }; 1373 1374 pdc: interrupt-controller@b220000 { 1375 compatible = "qcom,sdm670-pdc", "qcom,pdc"; 1376 reg = <0 0x0b220000 0 0x30000>; 1377 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, 1378 <54 534 24>, <79 559 15>, <94 609 15>, 1379 <115 630 7>; 1380 #interrupt-cells = <2>; 1381 interrupt-parent = <&intc>; 1382 interrupt-controller; 1383 }; 1384 1385 spmi_bus: spmi@c440000 { 1386 compatible = "qcom,spmi-pmic-arb"; 1387 reg = <0 0x0c440000 0 0x1100>, 1388 <0 0x0c600000 0 0x2000000>, 1389 <0 0x0e600000 0 0x100000>, 1390 <0 0x0e700000 0 0xa0000>, 1391 <0 0x0c40a000 0 0x26000>; 1392 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1393 interrupt-names = "periph_irq"; 1394 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1395 qcom,ee = <0>; 1396 qcom,channel = <0>; 1397 #address-cells = <2>; 1398 #size-cells = <0>; 1399 interrupt-controller; 1400 #interrupt-cells = <4>; 1401 }; 1402 1403 mdss: display-subsystem@ae00000 { 1404 compatible = "qcom,sdm670-mdss"; 1405 reg = <0 0x0ae00000 0 0x1000>; 1406 reg-names = "mdss"; 1407 1408 power-domains = <&dispcc MDSS_GDSC>; 1409 1410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1411 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1412 clock-names = "iface", "core"; 1413 1414 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1415 interrupt-controller; 1416 #interrupt-cells = <1>; 1417 1418 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, 1419 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; 1420 interconnect-names = "mdp0-mem", "mdp1-mem"; 1421 1422 iommus = <&apps_smmu 0x880 0x8>, 1423 <&apps_smmu 0xc80 0x8>; 1424 1425 #address-cells = <2>; 1426 #size-cells = <2>; 1427 ranges; 1428 1429 status = "disabled"; 1430 1431 mdss_mdp: display-controller@ae01000 { 1432 compatible = "qcom,sdm670-dpu"; 1433 reg = <0 0x0ae01000 0 0x8f000>, 1434 <0 0x0aeb0000 0 0x2008>; 1435 reg-names = "mdp", "vbif"; 1436 1437 clocks = <&gcc GCC_DISP_AXI_CLK>, 1438 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1439 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1440 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1441 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1442 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 1443 1444 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1445 assigned-clock-rates = <19200000>; 1446 operating-points-v2 = <&mdp_opp_table>; 1447 power-domains = <&rpmhpd SDM670_CX>; 1448 1449 interrupt-parent = <&mdss>; 1450 interrupts = <0>; 1451 1452 ports { 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 1456 port@0 { 1457 reg = <0>; 1458 dpu_intf0_out: endpoint { 1459 remote-endpoint = <&mdss_dsi0_in>; 1460 }; 1461 }; 1462 1463 port@1 { 1464 reg = <1>; 1465 dpu_intf1_out: endpoint { 1466 remote-endpoint = <&mdss_dsi1_in>; 1467 }; 1468 }; 1469 }; 1470 1471 mdp_opp_table: opp-table { 1472 compatible = "operating-points-v2"; 1473 1474 opp-19200000 { 1475 opp-hz = /bits/ 64 <19200000>; 1476 required-opps = <&rpmhpd_opp_min_svs>; 1477 }; 1478 1479 opp-171428571 { 1480 opp-hz = /bits/ 64 <171428571>; 1481 required-opps = <&rpmhpd_opp_low_svs>; 1482 }; 1483 1484 opp-358000000 { 1485 opp-hz = /bits/ 64 <358000000>; 1486 required-opps = <&rpmhpd_opp_svs_l1>; 1487 }; 1488 1489 opp-430000000 { 1490 opp-hz = /bits/ 64 <430000000>; 1491 required-opps = <&rpmhpd_opp_nom>; 1492 }; 1493 }; 1494 }; 1495 1496 mdss_dsi0: dsi@ae94000 { 1497 compatible = "qcom,sdm670-dsi-ctrl", 1498 "qcom,mdss-dsi-ctrl"; 1499 reg = <0 0x0ae94000 0 0x400>; 1500 reg-names = "dsi_ctrl"; 1501 1502 interrupt-parent = <&mdss>; 1503 interrupts = <4>; 1504 1505 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1506 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1507 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1508 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1509 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1510 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1511 clock-names = "byte", 1512 "byte_intf", 1513 "pixel", 1514 "core", 1515 "iface", 1516 "bus"; 1517 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1518 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1519 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1520 <&mdss_dsi0_phy 1>; 1521 1522 operating-points-v2 = <&dsi_opp_table>; 1523 power-domains = <&rpmhpd SDM670_CX>; 1524 1525 phys = <&mdss_dsi0_phy>; 1526 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 1530 status = "disabled"; 1531 1532 ports { 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 1536 port@0 { 1537 reg = <0>; 1538 mdss_dsi0_in: endpoint { 1539 remote-endpoint = <&dpu_intf0_out>; 1540 }; 1541 }; 1542 1543 port@1 { 1544 reg = <1>; 1545 mdss_dsi0_out: endpoint { 1546 }; 1547 }; 1548 }; 1549 }; 1550 1551 mdss_dsi0_phy: phy@ae94400 { 1552 compatible = "qcom,dsi-phy-10nm"; 1553 reg = <0 0x0ae94400 0 0x200>, 1554 <0 0x0ae94600 0 0x280>, 1555 <0 0x0ae94a00 0 0x1e0>; 1556 reg-names = "dsi_phy", 1557 "dsi_phy_lane", 1558 "dsi_pll"; 1559 1560 #clock-cells = <1>; 1561 #phy-cells = <0>; 1562 1563 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1564 <&rpmhcc RPMH_CXO_CLK>; 1565 clock-names = "iface", "ref"; 1566 1567 status = "disabled"; 1568 }; 1569 1570 mdss_dsi1: dsi@ae96000 { 1571 compatible = "qcom,sdm670-dsi-ctrl", 1572 "qcom,mdss-dsi-ctrl"; 1573 reg = <0 0x0ae96000 0 0x400>; 1574 reg-names = "dsi_ctrl"; 1575 1576 interrupt-parent = <&mdss>; 1577 interrupts = <5>; 1578 1579 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 1580 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 1581 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 1582 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 1583 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1584 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1585 clock-names = "byte", 1586 "byte_intf", 1587 "pixel", 1588 "core", 1589 "iface", 1590 "bus"; 1591 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 1592 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 1593 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1594 1595 operating-points-v2 = <&dsi_opp_table>; 1596 power-domains = <&rpmhpd SDM670_CX>; 1597 1598 phys = <&mdss_dsi1_phy>; 1599 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 1603 status = "disabled"; 1604 1605 ports { 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 1609 port@0 { 1610 reg = <0>; 1611 mdss_dsi1_in: endpoint { 1612 remote-endpoint = <&dpu_intf1_out>; 1613 }; 1614 }; 1615 1616 port@1 { 1617 reg = <1>; 1618 mdss_dsi1_out: endpoint { 1619 }; 1620 }; 1621 }; 1622 }; 1623 1624 mdss_dsi1_phy: phy@ae96400 { 1625 compatible = "qcom,dsi-phy-10nm"; 1626 reg = <0 0x0ae96400 0 0x200>, 1627 <0 0x0ae96600 0 0x280>, 1628 <0 0x0ae96a00 0 0x10e>; 1629 reg-names = "dsi_phy", 1630 "dsi_phy_lane", 1631 "dsi_pll"; 1632 1633 #clock-cells = <1>; 1634 #phy-cells = <0>; 1635 1636 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1637 <&rpmhcc RPMH_CXO_CLK>; 1638 clock-names = "iface", "ref"; 1639 1640 status = "disabled"; 1641 }; 1642 }; 1643 1644 dispcc: clock-controller@af00000 { 1645 compatible = "qcom,sdm845-dispcc"; 1646 reg = <0 0x0af00000 0 0x10000>; 1647 clocks = <&rpmhcc RPMH_CXO_CLK>, 1648 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1649 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1650 <&mdss_dsi0_phy 0>, 1651 <&mdss_dsi0_phy 1>, 1652 <&mdss_dsi1_phy 0>, 1653 <&mdss_dsi1_phy 1>, 1654 <0>, 1655 <0>; 1656 clock-names = "bi_tcxo", 1657 "gcc_disp_gpll0_clk_src", 1658 "gcc_disp_gpll0_div_clk_src", 1659 "dsi0_phy_pll_out_byteclk", 1660 "dsi0_phy_pll_out_dsiclk", 1661 "dsi1_phy_pll_out_byteclk", 1662 "dsi1_phy_pll_out_dsiclk", 1663 "dp_link_clk_divsel_ten", 1664 "dp_vco_divided_clk_src_mux"; 1665 #clock-cells = <1>; 1666 #reset-cells = <1>; 1667 #power-domain-cells = <1>; 1668 }; 1669 1670 apps_smmu: iommu@15000000 { 1671 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1672 reg = <0 0x15000000 0 0x80000>; 1673 #iommu-cells = <2>; 1674 #global-interrupts = <1>; 1675 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1740 }; 1741 1742 gladiator_noc: interconnect@17900000 { 1743 compatible = "qcom,sdm670-gladiator-noc"; 1744 reg = <0 0x17900000 0 0xd080>; 1745 #interconnect-cells = <2>; 1746 qcom,bcm-voters = <&apps_bcm_voter>; 1747 }; 1748 1749 apps_rsc: rsc@179c0000 { 1750 compatible = "qcom,rpmh-rsc"; 1751 reg = <0 0x179c0000 0 0x10000>, 1752 <0 0x179d0000 0 0x10000>, 1753 <0 0x179e0000 0 0x10000>; 1754 reg-names = "drv-0", "drv-1", "drv-2"; 1755 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1758 label = "apps_rsc"; 1759 qcom,tcs-offset = <0xd00>; 1760 qcom,drv-id = <2>; 1761 qcom,tcs-config = <ACTIVE_TCS 2>, 1762 <SLEEP_TCS 3>, 1763 <WAKE_TCS 3>, 1764 <CONTROL_TCS 1>; 1765 power-domains = <&CLUSTER_PD>; 1766 1767 apps_bcm_voter: bcm-voter { 1768 compatible = "qcom,bcm-voter"; 1769 }; 1770 1771 rpmhcc: clock-controller { 1772 compatible = "qcom,sdm670-rpmh-clk"; 1773 #clock-cells = <1>; 1774 clock-names = "xo"; 1775 clocks = <&xo_board>; 1776 }; 1777 1778 rpmhpd: power-controller { 1779 compatible = "qcom,sdm670-rpmhpd"; 1780 #power-domain-cells = <1>; 1781 operating-points-v2 = <&rpmhpd_opp_table>; 1782 1783 rpmhpd_opp_table: opp-table { 1784 compatible = "operating-points-v2"; 1785 1786 rpmhpd_opp_ret: opp1 { 1787 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1788 }; 1789 1790 rpmhpd_opp_min_svs: opp2 { 1791 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1792 }; 1793 1794 rpmhpd_opp_low_svs: opp3 { 1795 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1796 }; 1797 1798 rpmhpd_opp_svs: opp4 { 1799 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1800 }; 1801 1802 rpmhpd_opp_svs_l1: opp5 { 1803 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1804 }; 1805 1806 rpmhpd_opp_nom: opp6 { 1807 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1808 }; 1809 1810 rpmhpd_opp_nom_l1: opp7 { 1811 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1812 }; 1813 1814 rpmhpd_opp_nom_l2: opp8 { 1815 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1816 }; 1817 1818 rpmhpd_opp_turbo: opp9 { 1819 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1820 }; 1821 1822 rpmhpd_opp_turbo_l1: opp10 { 1823 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1824 }; 1825 }; 1826 }; 1827 }; 1828 1829 intc: interrupt-controller@17a00000 { 1830 compatible = "arm,gic-v3"; 1831 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1832 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1833 interrupt-controller; 1834 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1835 #interrupt-cells = <3>; 1836 }; 1837 1838 osm_l3: interconnect@17d41000 { 1839 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; 1840 reg = <0 0x17d41000 0 0x1400>; 1841 1842 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1843 clock-names = "xo", "alternate"; 1844 1845 #interconnect-cells = <1>; 1846 }; 1847 1848 cpufreq_hw: cpufreq@17d43000 { 1849 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw"; 1850 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 1851 reg-names = "freq-domain0", "freq-domain1"; 1852 1853 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1854 clock-names = "xo", "alternate"; 1855 1856 #freq-domain-cells = <1>; 1857 }; 1858 }; 1859}; 1860