1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen: chosen { }; 23 24 cpus { 25 #address-cells = <2>; 26 #size-cells = <0>; 27 28 CPU0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a55"; 31 reg = <0x0 0x0>; 32 clocks = <&cpufreq_hw 0>; 33 enable-method = "psci"; 34 power-domains = <&CPU_PD0>; 35 power-domain-names = "psci"; 36 qcom,freq-domains = <&cpufreq_hw 0>; 37 next-level-cache = <&L2_0>; 38 L2_0: l2-cache { 39 compatible = "cache"; 40 cache-level = <2>; 41 cache-unified; 42 next-level-cache = <&L3_0>; 43 L3_0: l3-cache { 44 compatible = "cache"; 45 cache-level = <3>; 46 cache-unified; 47 }; 48 }; 49 }; 50 51 CPU1: cpu@100 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x0 0x100>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 power-domains = <&CPU_PD1>; 58 power-domain-names = "psci"; 59 qcom,freq-domains = <&cpufreq_hw 0>; 60 next-level-cache = <&L2_100>; 61 L2_100: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 next-level-cache = <&L3_0>; 66 }; 67 }; 68 69 CPU2: cpu@200 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x200>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 power-domains = <&CPU_PD2>; 76 power-domain-names = "psci"; 77 qcom,freq-domains = <&cpufreq_hw 0>; 78 next-level-cache = <&L2_200>; 79 L2_200: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 cache-unified; 83 next-level-cache = <&L3_0>; 84 }; 85 }; 86 87 CPU3: cpu@300 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a55"; 90 reg = <0x0 0x300>; 91 clocks = <&cpufreq_hw 0>; 92 enable-method = "psci"; 93 power-domains = <&CPU_PD3>; 94 power-domain-names = "psci"; 95 qcom,freq-domains = <&cpufreq_hw 0>; 96 next-level-cache = <&L2_300>; 97 L2_300: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 cpu-map { 106 cluster0 { 107 core0 { 108 cpu = <&CPU0>; 109 }; 110 111 core1 { 112 cpu = <&CPU1>; 113 }; 114 115 core2 { 116 cpu = <&CPU2>; 117 }; 118 119 core3 { 120 cpu = <&CPU3>; 121 }; 122 }; 123 }; 124 }; 125 126 idle-states { 127 entry-method = "psci"; 128 129 CPU_OFF: cpu-sleep-0 { 130 compatible = "arm,idle-state"; 131 entry-latency-us = <274>; 132 exit-latency-us = <480>; 133 min-residency-us = <3934>; 134 arm,psci-suspend-param = <0x40000004>; 135 local-timer-stop; 136 }; 137 }; 138 139 domain-idle-states { 140 CLUSTER_SLEEP_0: cluster-sleep-0 { 141 compatible = "domain-idle-state"; 142 entry-latency-us = <584>; 143 exit-latency-us = <2332>; 144 min-residency-us = <6118>; 145 arm,psci-suspend-param = <0x41000044>; 146 }; 147 148 CLUSTER_SLEEP_1: cluster-sleep-1 { 149 compatible = "domain-idle-state"; 150 entry-latency-us = <2893>; 151 exit-latency-us = <4023>; 152 min-residency-us = <9987>; 153 arm,psci-suspend-param = <0x41003344>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-qdu1000", "qcom,scm"; 160 }; 161 }; 162 163 mc_virt: interconnect-0 { 164 compatible = "qcom,qdu1000-mc-virt"; 165 qcom,bcm-voters = <&apps_bcm_voter>; 166 #interconnect-cells = <2>; 167 }; 168 169 clk_virt: interconnect-1 { 170 compatible = "qcom,qdu1000-clk-virt"; 171 qcom,bcm-voters = <&apps_bcm_voter>; 172 #interconnect-cells = <2>; 173 }; 174 175 memory@80000000 { 176 device_type = "memory"; 177 /* We expect the bootloader to fill in the size */ 178 reg = <0x0 0x80000000 0x0 0x0>; 179 }; 180 181 pmu { 182 compatible = "arm,cortex-a55-pmu"; 183 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 psci { 187 compatible = "arm,psci-1.0"; 188 method = "smc"; 189 190 CPU_PD0: power-domain-cpu0 { 191 #power-domain-cells = <0>; 192 power-domains = <&CLUSTER_PD>; 193 domain-idle-states = <&CPU_OFF>; 194 }; 195 196 CPU_PD1: power-domain-cpu1 { 197 #power-domain-cells = <0>; 198 power-domains = <&CLUSTER_PD>; 199 domain-idle-states = <&CPU_OFF>; 200 }; 201 202 CPU_PD2: power-domain-cpu2 { 203 #power-domain-cells = <0>; 204 power-domains = <&CLUSTER_PD>; 205 domain-idle-states = <&CPU_OFF>; 206 }; 207 208 CPU_PD3: power-domain-cpu3 { 209 #power-domain-cells = <0>; 210 power-domains = <&CLUSTER_PD>; 211 domain-idle-states = <&CPU_OFF>; 212 }; 213 214 CLUSTER_PD: power-domain-cluster { 215 #power-domain-cells = <0>; 216 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; 217 }; 218 }; 219 220 reserved_memory: reserved-memory { 221 #address-cells = <2>; 222 #size-cells = <2>; 223 ranges; 224 225 hyp_mem: hyp@80000000 { 226 reg = <0x0 0x80000000 0x0 0x600000>; 227 no-map; 228 }; 229 230 xbl_dt_log_mem: xbl-dt-log@80600000 { 231 reg = <0x0 0x80600000 0x0 0x40000>; 232 no-map; 233 }; 234 235 xbl_ramdump_mem: xbl-ramdump@80640000 { 236 reg = <0x0 0x80640000 0x0 0x1c0000>; 237 no-map; 238 }; 239 240 aop_image_mem: aop-image@80800000 { 241 reg = <0x0 0x80800000 0x0 0x60000>; 242 no-map; 243 }; 244 245 aop_cmd_db_mem: aop-cmd-db@80860000 { 246 compatible = "qcom,cmd-db"; 247 reg = <0x0 0x80860000 0x0 0x20000>; 248 no-map; 249 }; 250 251 aop_config_mem: aop-config@80880000 { 252 reg = <0x0 0x80880000 0x0 0x20000>; 253 no-map; 254 }; 255 256 tme_crash_dump_mem: tme-crash-dump@808a0000 { 257 reg = <0x0 0x808a0000 0x0 0x40000>; 258 no-map; 259 }; 260 261 tme_log_mem: tme-log@808e0000 { 262 reg = <0x0 0x808e0000 0x0 0x4000>; 263 no-map; 264 }; 265 266 uefi_log_mem: uefi-log@808e4000 { 267 reg = <0x0 0x808e4000 0x0 0x10000>; 268 no-map; 269 }; 270 271 smem_mem: smem@80900000 { 272 compatible = "qcom,smem"; 273 reg = <0x0 0x80900000 0x0 0x200000>; 274 no-map; 275 hwlocks = <&tcsr_mutex 3>; 276 }; 277 278 cpucp_fw_mem: cpucp-fw@80b00000 { 279 reg = <0x0 0x80b00000 0x0 0x100000>; 280 no-map; 281 }; 282 283 xbl_sc_mem: memory@80c00000 { 284 reg = <0x0 0x80c00000 0x0 0x40000>; 285 no-map; 286 }; 287 288 tz_stat_mem: tz-stat@81d00000 { 289 reg = <0x0 0x81d00000 0x0 0x100000>; 290 no-map; 291 }; 292 293 tags_mem: tags@81e00000 { 294 reg = <0x0 0x81e00000 0x0 0x500000>; 295 no-map; 296 }; 297 298 qtee_mem: qtee@82300000 { 299 reg = <0x0 0x82300000 0x0 0x500000>; 300 no-map; 301 }; 302 303 ta_mem: ta@82800000 { 304 reg = <0x0 0x82800000 0x0 0xa00000>; 305 no-map; 306 }; 307 308 fs1_mem: fs1@83200000 { 309 reg = <0x0 0x83200000 0x0 0x400000>; 310 no-map; 311 }; 312 313 fs2_mem: fs2@83600000 { 314 reg = <0x0 0x83600000 0x0 0x400000>; 315 no-map; 316 }; 317 318 fs3_mem: fs3@83a00000 { 319 reg = <0x0 0x83a00000 0x0 0x400000>; 320 no-map; 321 }; 322 323 /* Linux kernel image is loaded at 0x83e00000 */ 324 325 ipa_fw_mem: ipa-fw@8be00000 { 326 reg = <0x0 0x8be00000 0x0 0x10000>; 327 no-map; 328 }; 329 330 ipa_gsi_mem: ipa-gsi@8be10000 { 331 reg = <0x0 0x8be10000 0x0 0x14000>; 332 no-map; 333 }; 334 335 mpss_mem: mpss@8c000000 { 336 reg = <0x0 0x8c000000 0x0 0x12c00000>; 337 no-map; 338 }; 339 340 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 { 341 reg = <0x0 0x9ec00000 0x0 0x80000>; 342 no-map; 343 }; 344 345 tenx_mem: tenx@a0000000 { 346 reg = <0x0 0xa0000000 0x0 0x19600000>; 347 no-map; 348 }; 349 350 oem_tenx_mem: oem-tenx@b9600000 { 351 reg = <0x0 0xb9600000 0x0 0x6a00000>; 352 no-map; 353 }; 354 355 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 { 356 reg = <0x0 0xc0000000 0x0 0x3200000>; 357 no-map; 358 }; 359 360 ipa_buffer_mem: ipa-buffer@c3200000 { 361 reg = <0x0 0xc3200000 0x0 0x12c00000>; 362 no-map; 363 }; 364 }; 365 366 soc: soc@0 { 367 compatible = "simple-bus"; 368 #address-cells = <2>; 369 #size-cells = <2>; 370 ranges = <0 0 0 0 0x10 0>; 371 dma-ranges = <0 0 0 0 0x10 0>; 372 373 gcc: clock-controller@80000 { 374 compatible = "qcom,qdu1000-gcc"; 375 reg = <0x0 0x80000 0x0 0x1f4200>; 376 clocks = <&rpmhcc RPMH_CXO_CLK>, 377 <&sleep_clk>, 378 <0>, 379 <0>, 380 <0>; 381 #clock-cells = <1>; 382 #reset-cells = <1>; 383 #power-domain-cells = <1>; 384 }; 385 386 ecpricc: clock-controller@280000 { 387 compatible = "qcom,qdu1000-ecpricc"; 388 reg = <0x0 0x00280000 0x0 0x31c00>; 389 clocks = <&rpmhcc RPMH_CXO_CLK>, 390 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, 391 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, 392 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, 393 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, 394 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, 395 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; 396 #clock-cells = <1>; 397 #reset-cells = <1>; 398 }; 399 400 gpi_dma0: dma-controller@900000 { 401 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 402 reg = <0x0 0x900000 0x0 0x60000>; 403 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 415 dma-channels = <12>; 416 dma-channel-mask = <0x3f>; 417 iommus = <&apps_smmu 0xf6 0x0>; 418 #dma-cells = <3>; 419 }; 420 421 qupv3_id_0: geniqup@9c0000 { 422 compatible = "qcom,geni-se-qup"; 423 reg = <0x0 0x9c0000 0x0 0x2000>; 424 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 425 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 426 clock-names = "m-ahb", "s-ahb"; 427 iommus = <&apps_smmu 0xe3 0x0>; 428 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 429 &clk_virt SLAVE_QUP_CORE_0 0>; 430 interconnect-names = "qup-core"; 431 432 #address-cells = <2>; 433 #size-cells = <2>; 434 ranges; 435 status = "disabled"; 436 437 uart0: serial@980000 { 438 compatible = "qcom,geni-uart"; 439 reg = <0x0 0x980000 0x0 0x4000>; 440 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 441 clock-names = "se"; 442 pinctrl-0 = <&qup_uart0_default>; 443 pinctrl-names = "default"; 444 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 445 status = "disabled"; 446 }; 447 448 i2c1: i2c@984000 { 449 compatible = "qcom,geni-i2c"; 450 reg = <0x0 0x984000 0x0 0x4000>; 451 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 452 clock-names = "se"; 453 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 454 pinctrl-0 = <&qup_i2c1_data_clk>; 455 pinctrl-names = "default"; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 spi1: spi@984000 { 462 compatible = "qcom,geni-spi"; 463 reg = <0x0 0x984000 0x0 0x4000>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 468 clock-names = "se"; 469 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 470 pinctrl-names = "default"; 471 status = "disabled"; 472 }; 473 474 i2c2: i2c@988000 { 475 compatible = "qcom,geni-i2c"; 476 reg = <0x0 0x988000 0x0 0x4000>; 477 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 478 clock-names = "se"; 479 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 480 pinctrl-0 = <&qup_i2c2_data_clk>; 481 pinctrl-names = "default"; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 status = "disabled"; 485 }; 486 487 spi2: spi@988000 { 488 compatible = "qcom,geni-spi"; 489 reg = <0x0 0x988000 0x0 0x4000>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 494 clock-names = "se"; 495 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 496 pinctrl-names = "default"; 497 status = "disabled"; 498 }; 499 500 i2c3: i2c@98c000 { 501 compatible = "qcom,geni-i2c"; 502 reg = <0x0 0x98c000 0x0 0x4000>; 503 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 504 clock-names = "se"; 505 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 506 pinctrl-0 = <&qup_i2c3_data_clk>; 507 pinctrl-names = "default"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 spi3: spi@98c000 { 514 compatible = "qcom,geni-spi"; 515 reg = <0x0 0x98c000 0x0 0x4000>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 520 clock-names = "se"; 521 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 522 pinctrl-names = "default"; 523 status = "disabled"; 524 }; 525 526 i2c4: i2c@990000 { 527 compatible = "qcom,geni-i2c"; 528 reg = <0x0 0x990000 0x0 0x4000>; 529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 530 clock-names = "se"; 531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 532 pinctrl-0 = <&qup_i2c4_data_clk>; 533 pinctrl-names = "default"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 539 spi4: spi@990000 { 540 compatible = "qcom,geni-spi"; 541 reg = <0x0 0x990000 0x0 0x4000>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 546 clock-names = "se"; 547 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 548 pinctrl-names = "default"; 549 status = "disabled"; 550 }; 551 552 i2c5: i2c@994000 { 553 compatible = "qcom,geni-i2c"; 554 reg = <0x0 0x994000 0x0 0x4000>; 555 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 556 clock-names = "se"; 557 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 558 pinctrl-0 = <&qup_i2c5_data_clk>; 559 pinctrl-names = "default"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 spi5: spi@994000 { 566 compatible = "qcom,geni-spi"; 567 reg = <0x0 0x994000 0x0 0x4000>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 572 clock-names = "se"; 573 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 574 pinctrl-names = "default"; 575 status = "disabled"; 576 }; 577 578 i2c6: i2c@998000 { 579 compatible = "qcom,geni-i2c"; 580 reg = <0x0 0x998000 0x0 0x4000>; 581 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 582 clock-names = "se"; 583 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 584 pinctrl-0 = <&qup_i2c6_data_clk>; 585 pinctrl-names = "default"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 spi6: spi@998000 { 592 compatible = "qcom,geni-spi"; 593 reg = <0x0 0x998000 0x0 0x4000>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 598 clock-names = "se"; 599 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 600 pinctrl-names = "default"; 601 status = "disabled"; 602 }; 603 604 uart7: serial@99c000 { 605 compatible = "qcom,geni-debug-uart"; 606 reg = <0x0 0x99c000 0x0 0x4000>; 607 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 608 clock-names = "se"; 609 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 610 pinctrl-names = "default"; 611 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 }; 615 616 gpi_dma1: dma-controller@a00000 { 617 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 618 reg = <0x0 0xa00000 0x0 0x60000>; 619 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 631 dma-channels = <12>; 632 dma-channel-mask = <0x3f>; 633 iommus = <&apps_smmu 0x116 0x0>; 634 #dma-cells = <3>; 635 }; 636 637 qupv3_id_1: geniqup@ac0000 { 638 compatible = "qcom,geni-se-qup"; 639 reg = <0x0 0xac0000 0x0 0x2000>; 640 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 641 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 642 clock-names = "m-ahb", "s-ahb"; 643 iommus = <&apps_smmu 0x103 0x0>; 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges; 647 status = "disabled"; 648 649 uart8: serial@a80000 { 650 compatible = "qcom,geni-uart"; 651 reg = <0x0 0xa80000 0x0 0x4000>; 652 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 653 clock-names = "se"; 654 pinctrl-0 = <&qup_uart8_default>; 655 pinctrl-names = "default"; 656 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 i2c9: i2c@a84000 { 663 compatible = "qcom,geni-i2c"; 664 reg = <0x0 0xa84000 0x0 0x4000>; 665 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 666 clock-names = "se"; 667 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 668 pinctrl-0 = <&qup_i2c9_data_clk>; 669 pinctrl-names = "default"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 spi9: spi@a84000 { 676 compatible = "qcom,geni-spi"; 677 reg = <0x0 0xa84000 0x0 0x4000>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 682 clock-names = "se"; 683 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 684 pinctrl-names = "default"; 685 status = "disabled"; 686 }; 687 688 i2c10: i2c@a88000 { 689 compatible = "qcom,geni-i2c"; 690 reg = <0x0 0xa88000 0x0 0x4000>; 691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 692 clock-names = "se"; 693 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 694 pinctrl-0 = <&qup_i2c10_data_clk>; 695 pinctrl-names = "default"; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 status = "disabled"; 699 }; 700 701 spi10: spi@a88000 { 702 compatible = "qcom,geni-spi"; 703 reg = <0x0 0xa88000 0x0 0x4000>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 708 clock-names = "se"; 709 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 710 pinctrl-names = "default"; 711 status = "disabled"; 712 }; 713 714 i2c11: i2c@a8c000 { 715 compatible = "qcom,geni-i2c"; 716 reg = <0x0 0xa8c000 0x0 0x4000>; 717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 718 clock-names = "se"; 719 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 720 pinctrl-0 = <&qup_i2c11_data_clk>; 721 pinctrl-names = "default"; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 status = "disabled"; 725 }; 726 727 spi11: spi@a8c000 { 728 compatible = "qcom,geni-spi"; 729 reg = <0x0 0xa8c000 0x0 0x4000>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 734 clock-names = "se"; 735 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 736 pinctrl-names = "default"; 737 status = "disabled"; 738 }; 739 740 i2c12: i2c@a90000 { 741 compatible = "qcom,geni-i2c"; 742 reg = <0x0 0xa90000 0x0 0x4000>; 743 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 744 clock-names = "se"; 745 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 746 pinctrl-0 = <&qup_i2c12_data_clk>; 747 pinctrl-names = "default"; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 spi12: spi@a90000 { 754 compatible = "qcom,geni-spi"; 755 reg = <0x0 0xa90000 0x0 0x4000>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 760 clock-names = "se"; 761 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 762 pinctrl-names = "default"; 763 status = "disabled"; 764 }; 765 766 i2c13: i2c@a94000 { 767 compatible = "qcom,geni-i2c"; 768 reg = <0x0 0xa94000 0x0 0x4000>; 769 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 770 clock-names = "se"; 771 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 772 pinctrl-0 = <&qup_i2c13_data_clk>; 773 pinctrl-names = "default"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 uart13: serial@a94000 { 780 compatible = "qcom,geni-uart"; 781 reg = <0x0 0xa94000 0x0 0x4000>; 782 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 783 clock-names = "se"; 784 pinctrl-0 = <&qup_uart13_default>; 785 pinctrl-names = "default"; 786 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi13: spi@a94000 { 793 compatible = "qcom,geni-spi"; 794 reg = <0x0 0xa94000 0x0 0x4000>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 799 clock-names = "se"; 800 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 801 pinctrl-names = "default"; 802 status = "disabled"; 803 }; 804 805 i2c14: i2c@a98000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0xa98000 0x0 0x4000>; 808 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 809 clock-names = "se"; 810 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 811 pinctrl-0 = <&qup_i2c14_data_clk>; 812 pinctrl-names = "default"; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 spi14: spi@a98000 { 819 compatible = "qcom,geni-spi"; 820 reg = <0x0 0xa98000 0x0 0x4000>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 825 clock-names = "se"; 826 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 827 pinctrl-names = "default"; 828 status = "disabled"; 829 }; 830 831 i2c15: i2c@a9c000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0x0 0xa9c000 0x0 0x4000>; 834 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 835 clock-names = "se"; 836 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 837 pinctrl-0 = <&qup_i2c15_data_clk>; 838 pinctrl-names = "default"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 spi15: spi@a9c000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0x0 0xa9c000 0x0 0x4000>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 851 clock-names = "se"; 852 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 853 pinctrl-names = "default"; 854 status = "disabled"; 855 }; 856 }; 857 858 system_noc: interconnect@1640000 { 859 compatible = "qcom,qdu1000-system-noc"; 860 reg = <0x0 0x1640000 0x0 0x45080>; 861 qcom,bcm-voters = <&apps_bcm_voter>; 862 #interconnect-cells = <2>; 863 }; 864 865 tcsr_mutex: hwlock@1f40000 { 866 compatible = "qcom,tcsr-mutex"; 867 reg = <0x0 0x1f40000 0x0 0x20000>; 868 #hwlock-cells = <1>; 869 }; 870 871 sdhc: mmc@8804000 { 872 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5"; 873 reg = <0x0 0x08804000 0x0 0x1000>, 874 <0x0 0x08805000 0x0 0x1000>; 875 reg-names = "hc", "cqhci"; 876 877 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "hc_irq", "pwr_irq"; 880 881 clocks = <&gcc GCC_SDCC5_AHB_CLK>, 882 <&gcc GCC_SDCC5_APPS_CLK>, 883 <&rpmhcc RPMH_CXO_CLK>; 884 clock-names = "iface", 885 "core", 886 "xo"; 887 888 resets = <&gcc GCC_SDCC5_BCR>; 889 890 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 891 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>; 892 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 893 power-domains = <&rpmhpd QDU1000_CX>; 894 operating-points-v2 = <&sdhc1_opp_table>; 895 896 iommus = <&apps_smmu 0x80 0x0>; 897 dma-coherent; 898 899 bus-width = <8>; 900 901 qcom,dll-config = <0x0007642c>; 902 qcom,ddr-config = <0x80040868>; 903 904 status = "disabled"; 905 906 sdhc1_opp_table: opp-table { 907 compatible = "operating-points-v2"; 908 909 opp-384000000 { 910 opp-hz = /bits/ 64 <384000000>; 911 required-opps = <&rpmhpd_opp_nom>; 912 opp-peak-kBps = <6528000 1652800>; 913 opp-avg-kBps = <400000 0>; 914 }; 915 }; 916 }; 917 918 usb_1_hsphy: phy@88e3000 { 919 compatible = "qcom,qdu1000-usb-hs-phy", 920 "qcom,usb-snps-hs-7nm-phy"; 921 reg = <0x0 0x088e3000 0x0 0x120>; 922 #phy-cells = <0>; 923 924 clocks =<&gcc GCC_USB2_CLKREF_EN>; 925 clock-names = "ref"; 926 927 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 928 929 status = "disabled"; 930 }; 931 932 usb_1_qmpphy: phy@88e5000 { 933 compatible = "qcom,qdu1000-qmp-usb3-uni-phy"; 934 reg = <0x0 0x088e5000 0x0 0x2000>; 935 936 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 937 <&gcc GCC_USB2_CLKREF_EN>, 938 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 939 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 940 clock-names = "aux", 941 "ref", 942 "com_aux", 943 "pipe"; 944 945 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 946 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 947 reset-names = "phy", 948 "phy_phy"; 949 950 #clock-cells = <0>; 951 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 952 953 #phy-cells = <0>; 954 955 status = "disabled"; 956 }; 957 958 usb_1: usb@a6f8800 { 959 compatible = "qcom,qdu1000-dwc3", "qcom,dwc3"; 960 reg = <0 0x0a6f8800 0 0x400>; 961 #address-cells = <2>; 962 #size-cells = <2>; 963 ranges; 964 965 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 966 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 967 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 968 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 969 clock-names = "cfg_noc", 970 "core", 971 "sleep", 972 "mock_utmi"; 973 974 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 975 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 976 assigned-clock-rates = <19200000>, <200000000>; 977 978 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 979 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 980 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 981 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 982 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 983 interrupt-names = "pwr_event", 984 "hs_phy_irq", 985 "dp_hs_phy_irq", 986 "dm_hs_phy_irq", 987 "ss_phy_irq"; 988 989 power-domains = <&gcc USB30_PRIM_GDSC>; 990 required-opps = <&rpmhpd_opp_nom>; 991 992 resets = <&gcc GCC_USB30_PRIM_BCR>; 993 994 interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 996 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 997 &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 998 999 interconnect-names = "usb-ddr", 1000 "apps-usb"; 1001 1002 status = "disabled"; 1003 1004 usb_1_dwc3: usb@a600000 { 1005 compatible = "snps,dwc3"; 1006 reg = <0 0x0a600000 0 0xcd00>; 1007 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1008 1009 iommus = <&apps_smmu 0xc0 0x0>; 1010 snps,dis_u2_susphy_quirk; 1011 snps,dis_enblslpm_quirk; 1012 phys = <&usb_1_hsphy>, 1013 <&usb_1_qmpphy>; 1014 phy-names = "usb2-phy", 1015 "usb3-phy"; 1016 1017 ports { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 port@0 { 1022 reg = <0>; 1023 1024 usb_1_dwc3_hs: endpoint { 1025 }; 1026 }; 1027 1028 port@1 { 1029 reg = <1>; 1030 1031 usb_1_dwc3_ss: endpoint { 1032 }; 1033 }; 1034 }; 1035 }; 1036 }; 1037 1038 pdc: interrupt-controller@b220000 { 1039 compatible = "qcom,qdu1000-pdc", "qcom,pdc"; 1040 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 1041 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 1042 <94 609 31>, <125 63 1>; 1043 #interrupt-cells = <2>; 1044 interrupt-parent = <&intc>; 1045 interrupt-controller; 1046 }; 1047 1048 spmi_bus: spmi@c400000 { 1049 compatible = "qcom,spmi-pmic-arb"; 1050 reg = <0x0 0xc400000 0x0 0x3000>, 1051 <0x0 0xc500000 0x0 0x400000>, 1052 <0x0 0xc440000 0x0 0x80000>, 1053 <0x0 0xc4c0000 0x0 0x10000>, 1054 <0x0 0xc42d000 0x0 0x4000>; 1055 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1056 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1057 interrupt-names = "periph_irq"; 1058 qcom,ee = <0>; 1059 qcom,channel = <0>; 1060 #address-cells = <2>; 1061 #size-cells = <0>; 1062 interrupt-controller; 1063 #interrupt-cells = <4>; 1064 }; 1065 1066 tlmm: pinctrl@f000000 { 1067 compatible = "qcom,qdu1000-tlmm"; 1068 reg = <0x0 0xf000000 0x0 0x1000000>; 1069 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1070 gpio-controller; 1071 #gpio-cells = <2>; 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 gpio-ranges = <&tlmm 0 0 151>; 1075 wakeup-parent = <&pdc>; 1076 1077 qup_uart0_default: qup-uart0-default-state { 1078 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 1079 function = "qup00"; 1080 }; 1081 1082 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1083 pins = "gpio10", "gpio11"; 1084 function = "qup01"; 1085 }; 1086 1087 qup_spi1_data_clk: qup-spi1-data-clk-state { 1088 pins = "gpio10", "gpio11", "gpio12"; 1089 function = "qup01"; 1090 }; 1091 1092 qup_spi1_cs: qup-spi1-cs-state { 1093 pins = "gpio13"; 1094 function = "gpio"; 1095 }; 1096 1097 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1098 pins = "gpio12", "gpio13"; 1099 function = "qup02"; 1100 }; 1101 1102 qup_spi2_data_clk: qup-spi2-data-clk-state { 1103 pins = "gpio12", "gpio13", "gpio10"; 1104 function = "qup02"; 1105 }; 1106 1107 qup_spi2_cs: qup-spi2-cs-state { 1108 pins = "gpio11"; 1109 function = "gpio"; 1110 }; 1111 1112 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1113 pins = "gpio14", "gpio15"; 1114 function = "qup03"; 1115 }; 1116 1117 qup_spi3_data_clk: qup-spi3-data-clk-state { 1118 pins = "gpio14", "gpio15", "gpio16"; 1119 function = "qup03"; 1120 }; 1121 1122 qup_spi3_cs: qup-spi3-cs-state { 1123 pins = "gpio17"; 1124 function = "gpio"; 1125 }; 1126 1127 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1128 pins = "gpio16", "gpio17"; 1129 function = "qup04"; 1130 }; 1131 1132 qup_spi4_data_clk: qup-spi4-data-clk-state { 1133 pins = "gpio16", "gpio17", "gpio14"; 1134 function = "qup04"; 1135 }; 1136 1137 qup_spi4_cs: qup-spi4-cs-state { 1138 pins = "gpio15"; 1139 function = "gpio"; 1140 }; 1141 1142 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1143 pins = "gpio130", "gpio131"; 1144 function = "qup05"; 1145 }; 1146 1147 qup_spi5_data_clk: qup-spi5-data-clk-state { 1148 pins = "gpio130", "gpio131", "gpio132"; 1149 function = "qup05"; 1150 }; 1151 1152 qup_spi5_cs: qup-spi5-cs-state { 1153 pins = "gpio133"; 1154 function = "gpio"; 1155 }; 1156 1157 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1158 pins = "gpio132", "gpio133"; 1159 function = "qup06"; 1160 }; 1161 1162 qup_spi6_data_clk: qup-spi6-data-clk-state { 1163 pins = "gpio132", "gpio133", "gpio130"; 1164 function = "qup06"; 1165 }; 1166 1167 qup_spi6_cs: qup-spi6-cs-state { 1168 pins = "gpio131"; 1169 function = "gpio"; 1170 }; 1171 1172 qup_uart7_rx: qup-uart7-rx-state { 1173 pins = "gpio135"; 1174 function = "qup07"; 1175 }; 1176 1177 qup_uart7_tx: qup-uart7-tx-state { 1178 pins = "gpio134"; 1179 function = "qup07"; 1180 }; 1181 1182 qup_uart8_default: qup-uart8-default-state { 1183 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 1184 function = "qup10"; 1185 }; 1186 1187 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 1188 pins = "gpio22", "gpio23"; 1189 function = "qup11"; 1190 }; 1191 1192 qup_spi9_data_clk: qup-spi9-data-clk-state { 1193 pins = "gpio22", "gpio23", "gpio24"; 1194 function = "qup11"; 1195 }; 1196 1197 qup_spi9_cs: qup-spi9-cs-state { 1198 pins = "gpio25"; 1199 function = "gpio"; 1200 }; 1201 1202 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 1203 pins = "gpio24", "gpio25"; 1204 function = "qup12"; 1205 }; 1206 1207 qup_spi10_data_clk: qup-spi10-data-clk-state { 1208 pins = "gpio24", "gpio25", "gpio22"; 1209 function = "qup12"; 1210 }; 1211 1212 qup_spi10_cs: qup-spi10-cs-state { 1213 pins = "gpio23"; 1214 function = "gpio"; 1215 }; 1216 1217 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 1218 pins = "gpio26", "gpio27"; 1219 function = "qup13"; 1220 }; 1221 1222 qup_spi11_data_clk: qup-spi11-data-clk-state { 1223 pins = "gpio26", "gpio27", "gpio28"; 1224 function = "qup13"; 1225 }; 1226 1227 qup_spi11_cs: qup-spi11-cs-state { 1228 pins = "gpio29"; 1229 function = "gpio"; 1230 }; 1231 1232 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 1233 pins = "gpio28", "gpio29"; 1234 function = "qup14"; 1235 }; 1236 1237 qup_spi12_data_clk: qup-spi12-data-clk-state { 1238 pins = "gpio28", "gpio29", "gpio26"; 1239 function = "qup14"; 1240 }; 1241 1242 qup_spi12_cs: qup-spi12-cs-state { 1243 pins = "gpio27"; 1244 function = "gpio"; 1245 }; 1246 1247 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 1248 pins = "gpio30", "gpio31"; 1249 function = "qup15"; 1250 }; 1251 1252 qup_spi13_data_clk: qup-spi13-data-clk-state { 1253 pins = "gpio30", "gpio31", "gpio32"; 1254 function = "qup15"; 1255 }; 1256 1257 qup_spi13_cs: qup-spi13-cs-state { 1258 pins = "gpio33"; 1259 function = "gpio"; 1260 }; 1261 1262 qup_uart13_default: qup-uart13-default-state { 1263 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 1264 function = "qup15"; 1265 }; 1266 1267 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 1268 pins = "gpio34", "gpio35"; 1269 function = "qup16"; 1270 }; 1271 1272 qup_spi14_data_clk: qup-spi14-data-clk-state { 1273 pins = "gpio34", "gpio35", "gpio36"; 1274 function = "qup16"; 1275 }; 1276 1277 qup_spi14_cs: qup-spi14-cs-state { 1278 pins = "gpio37", "gpio38"; 1279 function = "gpio"; 1280 }; 1281 1282 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 1283 pins = "gpio40", "gpio41"; 1284 function = "qup17"; 1285 }; 1286 1287 qup_spi15_data_clk: qup-spi15-data-clk-state { 1288 pins = "gpio40", "gpio41", "gpio30"; 1289 function = "qup17"; 1290 }; 1291 1292 qup_spi15_cs: qup-spi15-cs-state { 1293 pins = "gpio31"; 1294 function = "gpio"; 1295 }; 1296 1297 sdc_on_state: sdc-on-state { 1298 clk-pins { 1299 pins = "sdc1_clk"; 1300 drive-strength = <16>; 1301 bias-disable; 1302 }; 1303 1304 cmd-pins { 1305 pins = "sdc1_cmd"; 1306 drive-strength = <10>; 1307 bias-pull-up; 1308 }; 1309 1310 data-pins { 1311 pins = "sdc1_data"; 1312 drive-strength = <10>; 1313 bias-pull-up; 1314 }; 1315 1316 rclk-pins { 1317 pins = "sdc1_rclk"; 1318 bias-pull-down; 1319 }; 1320 }; 1321 1322 sdc_off_state: sdc-off-state { 1323 clk-pins { 1324 pins = "sdc1_clk"; 1325 drive-strength = <2>; 1326 bias-disable; 1327 }; 1328 1329 cmd-pins { 1330 pins = "sdc1_cmd"; 1331 drive-strength = <2>; 1332 bias-pull-up; 1333 }; 1334 1335 data-pins { 1336 pins = "sdc1_data"; 1337 drive-strength = <2>; 1338 bias-pull-up; 1339 }; 1340 1341 rclk-pins { 1342 pins = "sdc1_rclk"; 1343 bias-pull-down; 1344 }; 1345 }; 1346 }; 1347 1348 sram@14680000 { 1349 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd"; 1350 reg = <0 0x14680000 0 0x1000>; 1351 ranges = <0 0 0x14680000 0x1000>; 1352 #address-cells = <1>; 1353 #size-cells = <1>; 1354 1355 pil-reloc@94c { 1356 compatible = "qcom,pil-reloc-info"; 1357 reg = <0x94c 0xc8>; 1358 }; 1359 }; 1360 1361 apps_smmu: iommu@15000000 { 1362 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1363 reg = <0x0 0x15000000 0x0 0x100000>; 1364 #iommu-cells = <2>; 1365 #global-interrupts = <2>; 1366 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1415 }; 1416 1417 intc: interrupt-controller@17200000 { 1418 compatible = "arm,gic-v3"; 1419 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 1420 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ 1421 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1422 #interrupt-cells = <3>; 1423 interrupt-controller; 1424 #redistributor-regions = <1>; 1425 redistributor-stride = <0x0 0x20000>; 1426 }; 1427 1428 timer@17420000 { 1429 compatible = "arm,armv7-timer-mem"; 1430 reg = <0x0 0x17420000 0x0 0x1000>; 1431 #address-cells = <1>; 1432 #size-cells = <1>; 1433 ranges = <0x0 0x0 0x0 0x20000000>; 1434 1435 frame@17421000 { 1436 reg = <0x17421000 0x1000>, 1437 <0x17422000 0x1000>; 1438 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1440 frame-number = <0>; 1441 }; 1442 1443 frame@17423000 { 1444 reg = <0x17423000 0x1000>; 1445 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1446 frame-number = <1>; 1447 status = "disabled"; 1448 }; 1449 1450 frame@17425000 { 1451 reg = <0x17425000 0x1000>, 1452 <0x17426000 0x1000>; 1453 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1454 frame-number = <2>; 1455 status = "disabled"; 1456 }; 1457 1458 frame@17427000 { 1459 reg = <0x17427000 0x1000>; 1460 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1461 frame-number = <3>; 1462 status = "disabled"; 1463 }; 1464 1465 frame@17429000 { 1466 reg = <0x17429000 0x1000>; 1467 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1468 frame-number = <4>; 1469 status = "disabled"; 1470 }; 1471 1472 frame@1742b000 { 1473 reg = <0x1742b000 0x1000>; 1474 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1475 frame-number = <5>; 1476 status = "disabled"; 1477 }; 1478 1479 frame@1742d000 { 1480 reg = <0x1742d000 0x1000>; 1481 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1482 frame-number = <6>; 1483 status = "disabled"; 1484 }; 1485 }; 1486 1487 apps_rsc: rsc@17a00000 { 1488 compatible = "qcom,rpmh-rsc"; 1489 reg = <0x0 0x17a00000 0x0 0x10000>, 1490 <0x0 0x17a10000 0x0 0x10000>, 1491 <0x0 0x17a20000 0x0 0x10000>; 1492 reg-names = "drv-0", "drv-1", "drv-2"; 1493 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1496 qcom,tcs-offset = <0xd00>; 1497 qcom,drv-id = <2>; 1498 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1499 <WAKE_TCS 3>, <CONTROL_TCS 0>; 1500 label = "apps_rsc"; 1501 power-domains = <&CLUSTER_PD>; 1502 1503 apps_bcm_voter: bcm-voter { 1504 compatible = "qcom,bcm-voter"; 1505 }; 1506 1507 rpmhcc: clock-controller { 1508 compatible = "qcom,qdu1000-rpmh-clk"; 1509 clocks = <&xo_board>; 1510 clock-names = "xo"; 1511 #clock-cells = <1>; 1512 }; 1513 1514 rpmhpd: power-controller { 1515 compatible = "qcom,qdu1000-rpmhpd"; 1516 #power-domain-cells = <1>; 1517 operating-points-v2 = <&rpmhpd_opp_table>; 1518 1519 rpmhpd_opp_table: opp-table { 1520 compatible = "operating-points-v2"; 1521 1522 rpmhpd_opp_ret: opp1 { 1523 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1524 }; 1525 1526 rpmhpd_opp_min_svs: opp2 { 1527 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1528 }; 1529 1530 rpmhpd_opp_low_svs: opp3 { 1531 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1532 }; 1533 1534 rpmhpd_opp_svs: opp4 { 1535 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1536 }; 1537 1538 rpmhpd_opp_svs_l1: opp5 { 1539 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1540 }; 1541 1542 rpmhpd_opp_nom: opp6 { 1543 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1544 }; 1545 1546 rpmhpd_opp_nom_l1: opp7 { 1547 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1548 }; 1549 1550 rpmhpd_opp_nom_l2: opp8 { 1551 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1552 }; 1553 1554 rpmhpd_opp_turbo: opp9 { 1555 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1556 }; 1557 1558 rpmhpd_opp_turbo_l1: opp10 { 1559 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1560 }; 1561 }; 1562 }; 1563 }; 1564 1565 cpufreq_hw: cpufreq@17d90000 { 1566 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; 1567 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; 1568 reg-names = "freq-domain0", "freq-domain1"; 1569 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1570 clock-names = "xo", "alternate"; 1571 #freq-domain-cells = <1>; 1572 #clock-cells = <1>; 1573 }; 1574 1575 gem_noc: interconnect@19100000 { 1576 compatible = "qcom,qdu1000-gem-noc"; 1577 reg = <0x0 0x19100000 0x0 0xB8080>; 1578 qcom,bcm-voters = <&apps_bcm_voter>; 1579 #interconnect-cells = <2>; 1580 }; 1581 1582 system-cache-controller@19200000 { 1583 compatible = "qcom,qdu1000-llcc"; 1584 reg = <0 0x19200000 0 0x80000>, 1585 <0 0x19300000 0 0x80000>, 1586 <0 0x19600000 0 0x80000>, 1587 <0 0x19700000 0 0x80000>, 1588 <0 0x19a00000 0 0x80000>, 1589 <0 0x19b00000 0 0x80000>, 1590 <0 0x19e00000 0 0x80000>, 1591 <0 0x19f00000 0 0x80000>, 1592 <0 0x1a200000 0 0x80000>; 1593 reg-names = "llcc0_base", 1594 "llcc1_base", 1595 "llcc2_base", 1596 "llcc3_base", 1597 "llcc4_base", 1598 "llcc5_base", 1599 "llcc6_base", 1600 "llcc7_base", 1601 "llcc_broadcast_base"; 1602 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1603 1604 nvmem-cells = <&multi_chan_ddr>; 1605 nvmem-cell-names = "multi-chan-ddr"; 1606 }; 1607 1608 sec_qfprom: efuse@221c8000 { 1609 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; 1610 reg = <0 0x221c8000 0 0x1000>; 1611 #address-cells = <1>; 1612 #size-cells = <1>; 1613 1614 multi_chan_ddr: multi-chan-ddr@12b { 1615 reg = <0x12b 0x1>; 1616 bits = <0 2>; 1617 }; 1618 }; 1619 }; 1620 1621 timer { 1622 compatible = "arm,armv8-timer"; 1623 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1624 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1625 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1626 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1627 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1628 }; 1629}; 1630