1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * IPQ5018 SoC device tree source
4 *
5 * Copyright (c) 2023 The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/clock/qcom,apss-ipq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
11#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
12
13/ {
14	interrupt-parent = <&intc>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	clocks {
19		sleep_clk: sleep-clk {
20			compatible = "fixed-clock";
21			#clock-cells = <0>;
22		};
23
24		xo_board_clk: xo-board-clk {
25			compatible = "fixed-clock";
26			#clock-cells = <0>;
27		};
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		CPU0: cpu@0 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			reg = <0x0>;
38			enable-method = "psci";
39			next-level-cache = <&L2_0>;
40			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
41			operating-points-v2 = <&cpu_opp_table>;
42		};
43
44		CPU1: cpu@1 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			reg = <0x1>;
48			enable-method = "psci";
49			next-level-cache = <&L2_0>;
50			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
51			operating-points-v2 = <&cpu_opp_table>;
52		};
53
54		L2_0: l2-cache {
55			compatible = "cache";
56			cache-level = <2>;
57			cache-size = <0x80000>;
58			cache-unified;
59		};
60	};
61
62	cpu_opp_table: opp-table-cpu {
63		compatible = "operating-points-v2";
64		opp-shared;
65
66		opp-800000000 {
67			opp-hz = /bits/ 64 <800000000>;
68			opp-microvolt = <1100000>;
69			clock-latency-ns = <200000>;
70		};
71
72		opp-1008000000 {
73			opp-hz = /bits/ 64 <1008000000>;
74			opp-microvolt = <1100000>;
75			clock-latency-ns = <200000>;
76		};
77	};
78
79	firmware {
80		scm {
81			compatible = "qcom,scm-ipq5018", "qcom,scm";
82			qcom,sdi-enabled;
83		};
84	};
85
86	memory@40000000 {
87		device_type = "memory";
88		/* We expect the bootloader to fill in the size */
89		reg = <0x0 0x40000000 0x0 0x0>;
90	};
91
92	pmu {
93		compatible = "arm,cortex-a53-pmu";
94		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
95	};
96
97	psci {
98		compatible = "arm,psci-1.0";
99		method = "smc";
100	};
101
102	reserved-memory {
103		#address-cells = <2>;
104		#size-cells = <2>;
105		ranges;
106
107		bootloader@4a800000 {
108			reg = <0x0 0x4a800000 0x0 0x200000>;
109			no-map;
110		};
111
112		sbl@4aa00000 {
113			reg = <0x0 0x4aa00000 0x0 0x100000>;
114			no-map;
115		};
116
117		smem@4ab00000 {
118			compatible = "qcom,smem";
119			reg = <0x0 0x4ab00000 0x0 0x100000>;
120			no-map;
121
122			hwlocks = <&tcsr_mutex 3>;
123		};
124
125		tz_region: tz@4ac00000 {
126			reg = <0x0 0x4ac00000 0x0 0x200000>;
127			no-map;
128		};
129	};
130
131	soc: soc@0 {
132		compatible = "simple-bus";
133		#address-cells = <1>;
134		#size-cells = <1>;
135		ranges = <0 0 0 0xffffffff>;
136
137		usbphy0: phy@5b000 {
138			compatible = "qcom,ipq5018-usb-hsphy";
139			reg = <0x0005b000 0x120>;
140
141			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
142
143			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
144
145			#phy-cells = <0>;
146
147			status = "disabled";
148		};
149
150		tlmm: pinctrl@1000000 {
151			compatible = "qcom,ipq5018-tlmm";
152			reg = <0x01000000 0x300000>;
153			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
154			gpio-controller;
155			#gpio-cells = <2>;
156			gpio-ranges = <&tlmm 0 0 47>;
157			interrupt-controller;
158			#interrupt-cells = <2>;
159
160			uart1_pins: uart1-state {
161				pins = "gpio31", "gpio32", "gpio33", "gpio34";
162				function = "blsp1_uart1";
163				drive-strength = <8>;
164				bias-pull-down;
165			};
166		};
167
168		gcc: clock-controller@1800000 {
169			compatible = "qcom,gcc-ipq5018";
170			reg = <0x01800000 0x80000>;
171			clocks = <&xo_board_clk>,
172				 <&sleep_clk>,
173				 <0>,
174				 <0>,
175				 <0>,
176				 <0>,
177				 <0>,
178				 <0>,
179				 <0>;
180			#clock-cells = <1>;
181			#reset-cells = <1>;
182		};
183
184		tcsr_mutex: hwlock@1905000 {
185			compatible = "qcom,tcsr-mutex";
186			reg = <0x01905000 0x20000>;
187			#hwlock-cells = <1>;
188		};
189
190		sdhc_1: mmc@7804000 {
191			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
192			reg = <0x7804000 0x1000>;
193			reg-names = "hc";
194
195			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
196				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
197			interrupt-names = "hc_irq", "pwr_irq";
198
199			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
200				 <&gcc GCC_SDCC1_APPS_CLK>,
201				 <&xo_board_clk>;
202			clock-names = "iface", "core", "xo";
203			non-removable;
204			status = "disabled";
205		};
206
207		blsp_dma: dma-controller@7884000 {
208			compatible = "qcom,bam-v1.7.0";
209			reg = <0x07884000 0x1d000>;
210			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
211			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
212			clock-names = "bam_clk";
213			#dma-cells = <1>;
214			qcom,ee = <0>;
215		};
216
217		blsp1_uart1: serial@78af000 {
218			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
219			reg = <0x078af000 0x200>;
220			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
221			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
222				 <&gcc GCC_BLSP1_AHB_CLK>;
223			clock-names = "core", "iface";
224			status = "disabled";
225		};
226
227		blsp1_spi1: spi@78b5000 {
228			compatible = "qcom,spi-qup-v2.2.1";
229			#address-cells = <1>;
230			#size-cells = <0>;
231			reg = <0x078b5000 0x600>;
232			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
233			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
234				 <&gcc GCC_BLSP1_AHB_CLK>;
235			clock-names = "core", "iface";
236			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
237			dma-names = "tx", "rx";
238			status = "disabled";
239		};
240
241		usb: usb@8af8800 {
242			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
243			reg = <0x08af8800 0x400>;
244
245			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
246			interrupt-names = "hs_phy_irq";
247
248			clocks = <&gcc GCC_USB0_MASTER_CLK>,
249				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
250				 <&gcc GCC_USB0_SLEEP_CLK>,
251				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
252			clock-names = "core",
253				      "iface",
254				      "sleep",
255				      "mock_utmi";
256
257			resets = <&gcc GCC_USB0_BCR>;
258
259			qcom,select-utmi-as-pipe-clk;
260			#address-cells = <1>;
261			#size-cells = <1>;
262			ranges;
263
264			status = "disabled";
265
266			usb_dwc: usb@8a00000 {
267				compatible = "snps,dwc3";
268				reg = <0x08a00000 0xe000>;
269				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
270				clock-names = "ref";
271				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
272				phy-names = "usb2-phy";
273				phys = <&usbphy0>;
274				tx-fifo-resize;
275				snps,is-utmi-l1-suspend;
276				snps,hird-threshold = /bits/ 8 <0x0>;
277				snps,dis_u2_susphy_quirk;
278				snps,dis_u3_susphy_quirk;
279			};
280		};
281
282		intc: interrupt-controller@b000000 {
283			compatible = "qcom,msm-qgic2";
284			reg = <0x0b000000 0x1000>,  /* GICD */
285			      <0x0b002000 0x2000>,  /* GICC */
286			      <0x0b001000 0x1000>,  /* GICH */
287			      <0x0b004000 0x2000>;  /* GICV */
288			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
289			interrupt-controller;
290			#interrupt-cells = <3>;
291			#address-cells = <1>;
292			#size-cells = <1>;
293			ranges = <0 0x0b00a000 0x1ffa>;
294
295			v2m0: v2m@0 {
296				compatible = "arm,gic-v2m-frame";
297				reg = <0x00000000 0xff8>;
298				msi-controller;
299			};
300
301			v2m1: v2m@1000 {
302				compatible = "arm,gic-v2m-frame";
303				reg = <0x00001000 0xff8>;
304				msi-controller;
305			};
306		};
307
308		watchdog: watchdog@b017000 {
309			compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
310			reg = <0x0b017000 0x40>;
311			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
312			clocks = <&sleep_clk>;
313		};
314
315		apcs_glb: mailbox@b111000 {
316			compatible = "qcom,ipq5018-apcs-apps-global",
317				     "qcom,ipq6018-apcs-apps-global";
318			reg = <0x0b111000 0x1000>;
319			#clock-cells = <1>;
320			clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
321			clock-names = "pll", "xo", "gpll0";
322			#mbox-cells = <1>;
323		};
324
325		a53pll: clock@b116000 {
326			compatible = "qcom,ipq5018-a53pll";
327			reg = <0x0b116000 0x40>;
328			#clock-cells = <0>;
329			clocks = <&xo_board_clk>;
330			clock-names = "xo";
331		};
332
333		timer@b120000 {
334			compatible = "arm,armv7-timer-mem";
335			reg = <0x0b120000 0x1000>;
336			#address-cells = <1>;
337			#size-cells = <1>;
338			ranges;
339
340			frame@b120000 {
341				reg = <0x0b121000 0x1000>,
342				      <0x0b122000 0x1000>;
343				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
344					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
345				frame-number = <0>;
346			};
347
348			frame@b123000 {
349				reg = <0xb123000 0x1000>;
350				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
351				frame-number = <1>;
352				status = "disabled";
353			};
354
355			frame@b124000 {
356				frame-number = <2>;
357				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
358				reg = <0x0b124000 0x1000>;
359				status = "disabled";
360			};
361
362			frame@b125000 {
363				reg = <0x0b125000 0x1000>;
364				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
365				frame-number = <3>;
366				status = "disabled";
367			};
368
369			frame@b126000 {
370				reg = <0x0b126000 0x1000>;
371				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
372				frame-number = <4>;
373				status = "disabled";
374			};
375
376			frame@b127000 {
377				reg = <0x0b127000 0x1000>;
378				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
379				frame-number = <5>;
380				status = "disabled";
381			};
382
383			frame@b128000 {
384				reg = <0x0b128000 0x1000>;
385				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
386				frame-number = <6>;
387				status = "disabled";
388			};
389		};
390	};
391
392	timer {
393		compatible = "arm,armv8-timer";
394		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
395			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
396			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
397			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
398	};
399};
400