1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7986b.dtsi"
9
10/ {
11	model = "MediaTek MT7986b RFB";
12	chassis-type = "embedded";
13	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
14
15	aliases {
16		serial0 = &uart0;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@40000000 {
24		device_type = "memory";
25		reg = <0 0x40000000 0 0x40000000>;
26	};
27};
28
29&crypto {
30	status = "okay";
31};
32
33&eth {
34	status = "okay";
35
36	gmac0: mac@0 {
37		compatible = "mediatek,eth-mac";
38		reg = <0>;
39		phy-mode = "2500base-x";
40
41		fixed-link {
42			speed = <2500>;
43			full-duplex;
44			pause;
45		};
46	};
47
48	gmac1: mac@1 {
49		compatible = "mediatek,eth-mac";
50		reg = <1>;
51		phy-mode = "rgmii";
52
53		fixed-link {
54			speed = <1000>;
55			full-duplex;
56			pause;
57		};
58	};
59
60	mdio: mdio-bus {
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		switch@0 {
65			compatible = "mediatek,mt7531";
66			reg = <31>;
67			reset-gpios = <&pio 5 0>;
68
69			ports {
70				#address-cells = <1>;
71				#size-cells = <0>;
72
73				port@0 {
74					reg = <0>;
75					label = "lan0";
76				};
77
78				port@1 {
79					reg = <1>;
80					label = "lan1";
81				};
82
83				port@2 {
84					reg = <2>;
85					label = "lan2";
86				};
87
88				port@3 {
89					reg = <3>;
90					label = "lan3";
91				};
92
93				port@4 {
94					reg = <4>;
95					label = "lan4";
96				};
97
98				port@5 {
99					reg = <5>;
100					ethernet = <&gmac1>;
101					phy-mode = "rgmii";
102
103					fixed-link {
104						speed = <1000>;
105						full-duplex;
106						pause;
107					};
108				};
109
110				port@6 {
111					reg = <6>;
112					label = "cpu";
113					ethernet = <&gmac0>;
114					phy-mode = "2500base-x";
115
116					fixed-link {
117						speed = <2500>;
118						full-duplex;
119						pause;
120					};
121				};
122			};
123		};
124	};
125};
126
127&pio {
128	spi_flash_pins: spi-flash-pins {
129		mux {
130			function = "spi";
131			groups = "spi0", "spi0_wp_hold";
132		};
133	};
134
135	spic_pins: spic-pins {
136		mux {
137			function = "spi";
138			groups = "spi1_2";
139		};
140	};
141
142	wf_2g_5g_pins: wf-2g-5g-pins {
143		mux {
144			function = "wifi";
145			groups = "wf_2g", "wf_5g";
146		};
147		conf {
148			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
149			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
150			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
151			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
152			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
153			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
154			       "WF1_TOP_CLK", "WF1_TOP_DATA";
155			drive-strength = <4>;
156		};
157	};
158
159	wf_dbdc_pins: wf-dbdc-pins {
160		mux {
161			function = "wifi";
162			groups = "wf_dbdc";
163		};
164		conf {
165			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
166			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
167			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
168			       "WF0_TOP_CLK", "WF0_TOP_DATA";
169			drive-strength = <4>;
170		};
171	};
172};
173
174&spi0 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&spi_flash_pins>;
177	cs-gpios = <0>, <0>;
178	status = "okay";
179
180	spi_nand: flash@0 {
181		compatible = "spi-nand";
182		reg = <0>;
183		spi-max-frequency = <10000000>;
184		spi-tx-bus-width = <4>;
185		spi-rx-bus-width = <4>;
186	};
187};
188
189&spi1 {
190	pinctrl-names = "default";
191	pinctrl-0 = <&spic_pins>;
192	cs-gpios = <0>, <0>;
193	status = "okay";
194};
195
196&ssusb {
197	status = "okay";
198};
199
200&uart0 {
201	status = "okay";
202};
203
204&usb_phy {
205	status = "okay";
206};
207
208&wifi {
209	status = "okay";
210	pinctrl-names = "default", "dbdc";
211	pinctrl-0 = <&wf_2g_5g_pins>;
212	pinctrl-1 = <&wf_dbdc_pins>;
213};
214