1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/firmware/imx/rsrc.h>
8
9gpu0_subsys: bus@53000000 {
10	compatible = "simple-bus";
11	#address-cells = <1>;
12	#size-cells = <1>;
13	ranges = <0x53000000 0x0 0x53000000 0x1000000>;
14
15	gpu_3d0: gpu@53100000 {
16		compatible = "vivante,gc";
17		reg = <0x53100000 0x40000>;
18		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
19		clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
20			 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
21		clock-names = "core", "shader";
22		assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
23				  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
24		assigned-clock-rates = <700000000>, <850000000>;
25		power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
26	};
27};
28