1// SPDX-License-Identifier: GPL-2.0-or-later 2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ 3/* Based on code by myd_c335x.dts, MYiRtech.com */ 4/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ 5 6/dts-v1/; 7 8#include "am335x-myirtech-myc.dtsi" 9 10#include <dt-bindings/display/tda998x.h> 11#include <dt-bindings/input/input.h> 12 13/ { 14 model = "MYIR MYD-AM335X"; 15 compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; 16 17 chosen { 18 stdout-path = &uart0; 19 }; 20 21 clk12m: clk12m { 22 compatible = "fixed-clock"; 23 clock-frequency = <12000000>; 24 25 #clock-cells = <0>; 26 }; 27 28 gpio_buttons: gpio_buttons { 29 compatible = "gpio-keys"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&gpio_buttons_pins>; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 button1: button@0 { 36 reg = <0>; 37 label = "button1"; 38 linux,code = <BTN_1>; 39 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 40 }; 41 42 button2: button@1 { 43 reg = <1>; 44 label = "button2"; 45 linux,code = <BTN_2>; 46 gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 47 }; 48 }; 49 50 sound: sound { 51 compatible = "simple-audio-card"; 52 simple-audio-card,format = "i2s"; 53 simple-audio-card,bitclock-master = <&master_codec>; 54 simple-audio-card,frame-master = <&master_codec>; 55 56 simple-audio-card,cpu { 57 sound-dai = <&mcasp0>; 58 }; 59 60 master_codec: simple-audio-card,codec@1 { 61 sound-dai = <&sgtl5000>; 62 }; 63 64 simple-audio-card,codec@2 { 65 sound-dai = <&tda9988>; 66 }; 67 }; 68 69 vdd_5v0: vdd_5v0_reg { 70 compatible = "regulator-fixed"; 71 regulator-name = "vdd_5v0"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 regulator-always-on; 75 regulator-boot-on; 76 }; 77 78 vdd_3v3: vdd_3v3_reg { 79 compatible = "regulator-fixed"; 80 regulator-name = "vdd-3v3"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 regulator-always-on; 84 regulator-boot-on; 85 vin-supply = <&vdd_5v0>; 86 }; 87}; 88 89&cpsw_port2 { 90 status = "okay"; 91 phy-handle = <&phy1>; 92 phy-mode = "rgmii-id"; 93 ti,dual-emac-pvid = <2>; 94}; 95 96&davinci_mdio_sw { 97 phy1: ethernet-phy@6 { 98 reg = <6>; 99 eee-broken-1000t; 100 }; 101}; 102 103&mac_sw { 104 pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>; 105 pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>; 106 slaves = <2>; 107}; 108 109&dcan0 { 110 pinctrl-names = "default", "sleep"; 111 pinctrl-0 = <&dcan0_pins_default>; 112 pinctrl-1 = <&dcan0_pins_sleep>; 113 status = "okay"; 114}; 115 116&dcan1 { 117 pinctrl-names = "default", "sleep"; 118 pinctrl-0 = <&dcan1_pins_default>; 119 pinctrl-1 = <&dcan1_pins_sleep>; 120 status = "okay"; 121}; 122 123&ehrpwm0 { 124 pinctrl-names = "default", "sleep"; 125 pinctrl-0 = <&ehrpwm0_pins_default>; 126 pinctrl-1 = <&ehrpwm0_pins_sleep>; 127 status = "okay"; 128}; 129 130&epwmss0 { 131 status = "okay"; 132}; 133 134&i2c1 { 135 pinctrl-names = "default", "gpio", "sleep"; 136 pinctrl-0 = <&i2c1_pins_default>; 137 pinctrl-1 = <&i2c1_pins_gpio>; 138 pinctrl-2 = <&i2c1_pins_sleep>; 139 clock-frequency = <400000>; 140 scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 141 sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 142 status = "okay"; 143 144 sgtl5000: sgtl5000@a { 145 compatible = "fsl,sgtl5000"; 146 reg =<0xa>; 147 clocks = <&clk12m>; 148 micbias-resistor-k-ohms = <4>; 149 micbias-voltage-m-volts = <2250>; 150 VDDA-supply = <&vdd_3v3>; 151 VDDIO-supply = <&vdd_3v3>; 152 153 #sound-dai-cells = <0>; 154 }; 155 156 tda9988: tda9988@70 { 157 compatible = "nxp,tda998x"; 158 reg =<0x70>; 159 audio-ports = <TDA998x_I2S 1>; 160 161 #sound-dai-cells = <0>; 162 163 ports { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 port@0 { 168 reg = <0>; 169 170 hdmi_0: endpoint { 171 remote-endpoint = <&lcdc_0>; 172 }; 173 }; 174 }; 175 }; 176}; 177 178&lcdc { 179 pinctrl-names = "default", "sleep"; 180 pinctrl-0 = <&lcdc_pins_default>; 181 pinctrl-1 = <&lcdc_pins_sleep>; 182 blue-and-red-wiring = "straight"; 183 status = "okay"; 184 185 port { 186 lcdc_0: endpoint@0 { 187 remote-endpoint = <&hdmi_0>; 188 }; 189 }; 190}; 191 192&leds { 193 pinctrl-0 = <&led_mod_pins &leds_pins>; 194 195 led1: led1 { 196 label = "base:user1"; 197 gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; 198 color = <LED_COLOR_ID_GREEN>; 199 default-state = "off"; 200 }; 201 202 led2: led2 { 203 label = "base:user2"; 204 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 205 color = <LED_COLOR_ID_GREEN>; 206 default-state = "off"; 207 }; 208}; 209 210&mcasp0 { 211 pinctrl-names = "default", "sleep"; 212 pinctrl-0 = <&mcasp0_pins_default>; 213 pinctrl-1 = <&mcasp0_pins_sleep>; 214 op-mode = <0>; 215 tdm-slots = <2>; 216 serial-dir = <0 1 2 0>; 217 tx-num-evt = <32>; 218 rx-num-evt = <32>; 219 status = "okay"; 220 221 #sound-dai-cells = <0>; 222}; 223 224&mmc1 { 225 pinctrl-names = "default", "sleep"; 226 pinctrl-0 = <&mmc1_pins_default>; 227 pinctrl-1 = <&mmc1_pins_sleep>; 228 cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 229 bus-width = <4>; 230 vmmc-supply = <&vdd_3v3>; 231 status = "okay"; 232}; 233 234&nand0 { 235 nand_parts: partitions { 236 compatible = "fixed-partitions"; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 240 partition@0 { 241 label = "MLO"; 242 reg = <0x00000 0x20000>; 243 }; 244 245 partition@80000 { 246 label = "boot"; 247 reg = <0x80000 0x100000>; 248 }; 249 }; 250}; 251 252&tscadc { 253 status = "okay"; 254 255 adc: adc { 256 ti,adc-channels = <0 1 2 3 4 5 6>; 257 }; 258}; 259 260&uart0 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&uart0_pins>; 263 status = "okay"; 264}; 265 266&uart1 { 267 pinctrl-names = "default", "sleep"; 268 pinctrl-0 = <&uart1_pins_default>; 269 pinctrl-1 = <&uart1_pins_sleep>; 270 linux,rs485-enabled-at-boot-time; 271 status = "okay"; 272}; 273 274&uart2 { 275 pinctrl-names = "default", "sleep"; 276 pinctrl-0 = <&uart2_pins_default>; 277 pinctrl-1 = <&uart2_pins_sleep>; 278 status = "okay"; 279}; 280 281&usb { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&usb_pins>; 284}; 285 286&usb0 { 287 dr_mode = "otg"; 288}; 289 290&usb0_phy { 291 vcc-supply = <&vdd_5v0>; 292}; 293 294&usb1 { 295 dr_mode = "host"; 296}; 297 298&usb1_phy { 299 vcc-supply = <&vdd_5v0>; 300}; 301 302&vdd_mod { 303 vin-supply = <&vdd_3v3>; 304}; 305 306&am33xx_pinmux { 307 dcan0_pins_default: dcan0-default-pins { 308 pinctrl-single,pins = < 309 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ 310 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ 311 >; 312 }; 313 314 dcan0_pins_sleep: dcan0-sleep-pins { 315 pinctrl-single,pins = < 316 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 317 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 318 >; 319 }; 320 321 dcan1_pins_default: dcan1-default-pins { 322 pinctrl-single,pins = < 323 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ 324 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ 325 >; 326 }; 327 328 dcan1_pins_sleep: dcan1-sleep-pins { 329 pinctrl-single,pins = < 330 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 331 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 332 >; 333 }; 334 335 ehrpwm0_pins_default: ehrpwm0-default-pins { 336 pinctrl-single,pins = < 337 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ 338 >; 339 }; 340 341 ehrpwm0_pins_sleep: ehrpwm0-sleep-pins { 342 pinctrl-single,pins = < 343 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 344 >; 345 }; 346 347 eth_slave2_pins_default: eth-slave2-default-pins { 348 pinctrl-single,pins = < 349 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ 350 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ 351 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */ 352 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */ 353 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */ 354 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */ 355 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */ 356 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */ 357 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */ 358 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */ 359 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */) 360 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */) 361 >; 362 }; 363 364 eth_slave2_pins_sleep: eth-slave2-sleep-pins { 365 pinctrl-single,pins = < 366 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) 367 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) 368 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) 369 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) 370 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) 371 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) 372 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) 373 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) 374 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) 375 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) 376 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) 377 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) 378 >; 379 }; 380 381 gpio_buttons_pins: gpio-buttons-pins { 382 pinctrl-single,pins = < 383 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ 384 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ 385 >; 386 }; 387 388 i2c1_pins_default: i2c1-default-pins { 389 pinctrl-single,pins = < 390 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ 391 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ 392 >; 393 }; 394 395 i2c1_pins_gpio: i2c1-gpio-pins { 396 pinctrl-single,pins = < 397 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ 398 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ 399 >; 400 }; 401 402 i2c1_pins_sleep: i2c1-sleep-pins { 403 pinctrl-single,pins = < 404 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) 405 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) 406 >; 407 }; 408 409 lcdc_pins_default: lcdc-default-pins { 410 pinctrl-single,pins = < 411 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ 412 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ 413 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */ 414 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */ 415 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */ 416 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */ 417 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */ 418 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */ 419 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */ 420 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */ 421 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */ 422 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */ 423 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */ 424 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */ 425 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */ 426 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */ 427 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */ 428 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */ 429 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */ 430 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */ 431 >; 432 }; 433 434 lcdc_pins_sleep: lcdc-sleep-pins { 435 pinctrl-single,pins = < 436 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) 437 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) 438 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) 439 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) 440 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) 441 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) 442 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) 443 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) 444 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) 445 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) 446 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) 447 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) 448 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) 449 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) 450 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) 451 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) 452 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) 453 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) 454 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 455 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 456 >; 457 }; 458 459 leds_pins: leds-pins { 460 pinctrl-single,pins = < 461 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ 462 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ 463 >; 464 }; 465 466 mcasp0_pins_default: mcasp0-default-pins { 467 pinctrl-single,pins = < 468 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ 469 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ 470 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */ 471 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */ 472 >; 473 }; 474 475 mcasp0_pins_sleep: mcasp0-sleep-pins { 476 pinctrl-single,pins = < 477 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) 478 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) 479 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) 480 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) 481 >; 482 }; 483 484 mmc1_pins_default: mmc1-default-pins { 485 pinctrl-single,pins = < 486 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ 487 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ 488 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */ 489 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */ 490 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */ 491 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */ 492 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */ 493 >; 494 }; 495 496 mmc1_pins_sleep: mmc1-sleep-pins { 497 pinctrl-single,pins = < 498 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) 499 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) 500 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0) 501 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0) 502 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 503 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0) 504 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) 505 >; 506 }; 507 508 uart0_pins: uart0-pins { 509 pinctrl-single,pins = < 510 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ 511 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ 512 >; 513 }; 514 515 uart1_pins_default: uart1-default-pins { 516 pinctrl-single,pins = < 517 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ 518 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ 519 >; 520 }; 521 522 uart1_pins_sleep: uart1-sleep-pins { 523 pinctrl-single,pins = < 524 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) 525 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) 526 >; 527 }; 528 529 uart2_pins_default: uart2-default-pins { 530 pinctrl-single,pins = < 531 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ 532 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ 533 >; 534 }; 535 536 uart2_pins_sleep: uart2-sleep-pins { 537 pinctrl-single,pins = < 538 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) 539 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 540 >; 541 }; 542 543 usb_pins: usb-pins { 544 pinctrl-single,pins = < 545 AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ 546 AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ 547 >; 548 }; 549}; 550