1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include "stm32mp131.dtsi"
8
9/ {
10	soc {
11		m_can1: can@4400e000 {
12			compatible = "bosch,m_can";
13			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
14			reg-names = "m_can", "message_ram";
15			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
16				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
17			interrupt-names = "int0", "int1";
18			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
19			clock-names = "hclk", "cclk";
20			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
21			status = "disabled";
22		};
23
24		m_can2: can@4400f000 {
25			compatible = "bosch,m_can";
26			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
27			reg-names = "m_can", "message_ram";
28			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
29				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
30			interrupt-names = "int0", "int1";
31			clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
32			clock-names = "hclk", "cclk";
33			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
34			status = "disabled";
35		};
36	};
37};
38
39&etzpc {
40	adc_1: adc@48003000 {
41		compatible = "st,stm32mp13-adc-core";
42		reg = <0x48003000 0x400>;
43		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
44		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
45		clock-names = "bus", "adc";
46		interrupt-controller;
47		#interrupt-cells = <1>;
48		#address-cells = <1>;
49		#size-cells = <0>;
50		access-controllers = <&etzpc 32>;
51		status = "disabled";
52
53		adc1: adc@0 {
54			compatible = "st,stm32mp13-adc";
55			#io-channel-cells = <1>;
56			#address-cells = <1>;
57			#size-cells = <0>;
58			reg = <0x0>;
59			interrupt-parent = <&adc_1>;
60			interrupts = <0>;
61			dmas = <&dmamux1 9 0x400 0x80000001>;
62			dma-names = "rx";
63			status = "disabled";
64
65			channel@18 {
66				reg = <18>;
67				label = "vrefint";
68			};
69		};
70	};
71
72	ethernet2: ethernet@5800e000 {
73		compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
74		reg = <0x5800e000 0x2000>;
75		reg-names = "stmmaceth";
76		interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
77		interrupt-names = "macirq";
78		clock-names = "stmmaceth",
79			      "mac-clk-tx",
80			      "mac-clk-rx",
81			      "ethstp",
82			      "eth-ck";
83		clocks = <&rcc ETH2MAC>,
84			 <&rcc ETH2TX>,
85			 <&rcc ETH2RX>,
86			 <&rcc ETH2STP>,
87			 <&rcc ETH2CK_K>;
88		st,syscon = <&syscfg 0x4 0xff000000>;
89		snps,mixed-burst;
90		snps,pbl = <2>;
91		snps,axi-config = <&stmmac_axi_config_2>;
92		snps,tso;
93		access-controllers = <&etzpc 49>;
94		status = "disabled";
95
96		stmmac_axi_config_2: stmmac-axi-config {
97			snps,blen = <0 0 0 0 16 8 4>;
98			snps,rd_osr_lmt = <0x7>;
99			snps,wr_osr_lmt = <0x7>;
100		};
101	};
102};
103