1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,rpmsg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP Audio RPMSG CPU DAI Controller
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  fsl_rpmsg is a virtual audio device. Mapping to real hardware devices
14  are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
15  Linux side is a device which provides audio service by rpmsg channel.
16  We can create different sound cards which access different hardwares
17  such as SAI, MICFIL, .etc through building rpmsg channels between
18  Cortex-A and Cortex-M.
19
20allOf:
21  - $ref: sound-card-common.yaml#
22
23properties:
24  compatible:
25    enum:
26      - fsl,imx7ulp-rpmsg-audio
27      - fsl,imx8mn-rpmsg-audio
28      - fsl,imx8mm-rpmsg-audio
29      - fsl,imx8mp-rpmsg-audio
30      - fsl,imx8ulp-rpmsg-audio
31      - fsl,imx93-rpmsg-audio
32      - fsl,imx95-rpmsg-audio
33
34  clocks:
35    items:
36      - description: Peripheral clock for register access
37      - description: Master clock
38      - description: DMA clock for DMA register access
39      - description: Parent clock for multiple of 8kHz sample rates
40      - description: Parent clock for multiple of 11kHz sample rates
41
42  clock-names:
43    items:
44      - const: ipg
45      - const: mclk
46      - const: dma
47      - const: pll8k
48      - const: pll11k
49
50  power-domains:
51    description:
52      List of phandle and PM domain specifier as documented in
53      Documentation/devicetree/bindings/power/power_domain.txt
54    maxItems: 1
55
56  memory-region:
57    maxItems: 1
58    description:
59      phandle to a node describing reserved memory (System RAM memory)
60      The M core can't access all the DDR memory space on some platform,
61      So reserved a specific memory for dma buffer which M core can
62      access.
63      (see bindings/reserved-memory/reserved-memory.txt)
64
65  audio-codec:
66    $ref: /schemas/types.yaml#/definitions/phandle
67    description: The phandle to a node of audio codec
68
69  fsl,enable-lpa:
70    $ref: /schemas/types.yaml#/definitions/flag
71    description: enable low power audio path.
72
73  fsl,rpmsg-out:
74    $ref: /schemas/types.yaml#/definitions/flag
75    description: |
76      This is a boolean property. If present, the transmitting function
77      will be enabled.
78
79  fsl,rpmsg-in:
80    $ref: /schemas/types.yaml#/definitions/flag
81    description: |
82      This is a boolean property. If present, the receiving function
83      will be enabled.
84
85  fsl,rpmsg-channel-name:
86    $ref: /schemas/types.yaml#/definitions/string
87    description: |
88      A string property to assign rpmsg channel this sound card sits on.
89      This property can be omitted if there is only one sound card and it sits
90      on "rpmsg-audio-channel".
91    enum:
92      - rpmsg-audio-channel
93      - rpmsg-micfil-channel
94
95required:
96  - compatible
97
98unevaluatedProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/clock/imx8mn-clock.h>
103
104    rpmsg_audio: rpmsg_audio {
105        compatible = "fsl,imx8mn-rpmsg-audio";
106        model = "wm8524-audio";
107        fsl,enable-lpa;
108        fsl,rpmsg-out;
109        clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
110                 <&clk IMX8MN_CLK_SAI3_ROOT>,
111                 <&clk IMX8MN_CLK_SDMA3_ROOT>,
112                 <&clk IMX8MN_AUDIO_PLL1_OUT>,
113                 <&clk IMX8MN_AUDIO_PLL2_OUT>;
114        clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
115    };
116
117  - |
118    #include <dt-bindings/clock/imx8mm-clock.h>
119
120    rpmsg_micfil: audio-controller {
121        compatible = "fsl,imx8mm-rpmsg-audio";
122        model = "micfil-audio";
123        fsl,rpmsg-channel-name = "rpmsg-micfil-channel";
124        fsl,enable-lpa;
125        fsl,rpmsg-in;
126        clocks = <&clk IMX8MM_CLK_PDM_IPG>,
127                 <&clk IMX8MM_CLK_PDM_ROOT>,
128                 <&clk IMX8MM_CLK_SDMA3_ROOT>,
129                 <&clk IMX8MM_AUDIO_PLL1_OUT>,
130                 <&clk IMX8MM_AUDIO_PLL2_OUT>;
131        clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
132    };
133
134...
135