| /linux-6.12.1/arch/mips/pci/ |
| D | pcie-octeon.c | 95 static int cvmx_pcie_rc_initialize(int pcie_port);
105 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port) in cvmx_pcie_get_io_base_address() argument
114 pcie_addr.io.port = pcie_port; in cvmx_pcie_get_io_base_address()
126 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port) in cvmx_pcie_get_io_size() argument
139 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port) in cvmx_pcie_get_mem_base_address() argument
146 pcie_addr.mem.subdid = 3 + pcie_port; in cvmx_pcie_get_mem_base_address()
158 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port) in cvmx_pcie_get_mem_size() argument
172 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) in cvmx_pcie_cfgx_read() argument
178 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); in cvmx_pcie_cfgx_read()
179 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); in cvmx_pcie_cfgx_read()
[all …]
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| /linux-6.12.1/arch/arm/mach-dove/ |
| D | pcie.c | 22 struct pcie_port { struct
31 static struct pcie_port pcie_port[2]; argument
37 struct pcie_port *pp; in dove_pcie_setup()
43 pp = &pcie_port[nr]; in dove_pcie_setup()
81 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) in pcie_valid_config()
97 struct pcie_port *pp = sys->private_data; in pcie_rd_conf()
117 struct pcie_port *pp = sys->private_data; in pcie_wr_conf()
180 struct pcie_port *pp = sys->private_data; in dove_pcie_map_irq()
197 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; in add_pcie_port()
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| /linux-6.12.1/arch/arm/mach-mv78xx0/ |
| D | pcie.c | 23 struct pcie_port { struct
33 static struct pcie_port pcie_port[8]; argument
75 struct pcie_port *pp = pcie_port + i; in mv78xx0_pcie_preinit()
100 struct pcie_port *pp; in mv78xx0_pcie_setup()
106 pp = &pcie_port[nr]; in mv78xx0_pcie_setup()
125 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) in pcie_valid_config()
141 struct pcie_port *pp = sys->private_data; in pcie_rd_conf()
161 struct pcie_port *pp = sys->private_data; in pcie_wr_conf()
224 struct pcie_port *pp = sys->private_data; in mv78xx0_pcie_map_irq()
242 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; in add_pcie_port()
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| /linux-6.12.1/drivers/net/ethernet/cavium/liquidio/ |
| D | cn66xx_device.c | 89 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
91 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
112 r64 = octeon_read_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
114 octeon_write_csr64(oct, CN6XXX_SLI_S2M_PORTX_CTL(oct->pcie_port), r64); in lio_cn6xxx_setup_pcie_mrrs()
117 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
119 lio_pci_writeq(oct, r64, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
167 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_input_regs()
200 (oct->pcie_port * 0x5555555555555555ULL)); in lio_cn6xxx_setup_global_output_regs()
420 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
422 CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
[all …]
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| D | cn23xx_pf_device.c | 82 "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port, in cn23xx_dump_pf_initialized_regs()
83 CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port), in cn23xx_dump_pf_initialized_regs()
84 lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))); in cn23xx_dump_pf_initialized_regs()
88 "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port, in cn23xx_dump_pf_initialized_regs()
89 CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)), in cn23xx_dump_pf_initialized_regs()
91 oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)))); in cn23xx_dump_pf_initialized_regs()
303 u16 mac_no = oct->pcie_port; in cn23xx_setup_global_mac_regs()
423 reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS; in cn23xx_pf_setup_global_input_regs()
712 u16 mac_no = oct->pcie_port; in cn23xx_setup_pf_mbox()
1048 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_setup()
[all …]
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| D | octeon_nic.c | 68 rdp->pcie_port = oct->pcie_port; in octeon_alloc_soft_command_resp()
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| D | request_manager.c | 632 rdp->pcie_port = oct->pcie_port; in octeon_prepare_soft_command()
669 rdp->pcie_port = oct->pcie_port; in octeon_prepare_soft_command()
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| D | lio_ethtool.c | 2553 reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2556 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2560 reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2563 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2567 reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2570 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2579 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2583 oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2586 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2590 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
[all …]
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| D | liquidio_common.h | 565 u64 pcie_port:3; member
569 u64 pcie_port:3;
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| D | octeon_device.h | 463 u16 pcie_port; member
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| /linux-6.12.1/drivers/phy/hisilicon/ |
| D | phy-hi3670-pcie.c | 556 struct device_node *pcie_port; in hi3670_pcie_get_resources_from_pcie() local
560 pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); in hi3670_pcie_get_resources_from_pcie()
561 if (!pcie_port) { in hi3670_pcie_get_resources_from_pcie()
567 pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port); in hi3670_pcie_get_resources_from_pcie()
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| /linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep/ |
| D | octep_cnxk_pf.c | 211 if (oct->pcie_port) in octep_configure_ring_mapping_cnxk_pf()
242 val = octep_read_csr64(oct, CNXK_SDP_MAC_PF_RING_CTL(oct->pcie_port)); in octep_init_config_cnxk_pf()
243 dev_info(&pdev->dev, "SDP_MAC_PF_RING_CTL[%d]:0x%llx\n", oct->pcie_port, val); in octep_init_config_cnxk_pf()
911 oct->pcie_port = octep_read_csr64(oct, CNXK_SDP_MAC_NUMBER) & 0xff; in octep_device_setup_cnxk_pf()
913 "Octeon device using PCIE Port %d\n", oct->pcie_port); in octep_device_setup_cnxk_pf()
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| D | octep_cn9k_pf.c | 188 if (oct->pcie_port) in octep_configure_ring_mapping_cn93_pf()
218 val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port)); in octep_init_config_cn93_pf()
891 oct->pcie_port = octep_read_csr64(oct, CN93_SDP_MAC_NUMBER) & 0xff; in octep_device_setup_cn93_pf()
893 "Octeon device using PCIE Port %d\n", oct->pcie_port); in octep_device_setup_cn93_pf()
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| D | octep_main.h | 266 u16 pcie_port; member
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| /linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep_vf/ |
| D | octep_vf_main.h | 255 u16 pcie_port; member
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a.dtsi | 413 phys = <&pcie_port PHY_TYPE_PCIE>;
439 pcie_port: pcie-phy@11c00000 { label
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