82 		"CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port,  in cn23xx_dump_pf_initialized_regs()
83 		CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),  in cn23xx_dump_pf_initialized_regs()
84 		lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port)));  in cn23xx_dump_pf_initialized_regs()
88 		"CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port,  in cn23xx_dump_pf_initialized_regs()
89 		CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)),  in cn23xx_dump_pf_initialized_regs()
91 			oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));  in cn23xx_dump_pf_initialized_regs()
303 	u16 mac_no = oct->pcie_port;  in cn23xx_setup_global_mac_regs()
423 		reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;  in cn23xx_pf_setup_global_input_regs()
712 	u16 mac_no = oct->pcie_port;  in cn23xx_setup_pf_mbox()
1048 			oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
1051 			       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
1053 			oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
1062 		       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
1065 		   oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)));  in cn23xx_bar1_idx_setup()
1071 		       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_write()
1077 	    oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_read()
1148 	oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;  in cn23xx_get_pcie_qlmport()
1151 		oct->pcie_port);  in cn23xx_get_pcie_qlmport()
1243 	    CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);  in cn23xx_setup_reg_address()
1246 	    CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);  in cn23xx_setup_reg_address()