Searched refs:mmIH_RB_WPTR (Results 1 – 16 of 16) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | cz_ih.c | 90 WREG32(mmIH_RB_WPTR, 0); in cz_ih_disable_interrupts()
145 WREG32(mmIH_RB_WPTR, 0); in cz_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
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| D | iceland_ih.c | 90 WREG32(mmIH_RB_WPTR, 0); in iceland_ih_disable_interrupts()
145 WREG32(mmIH_RB_WPTR, 0); in iceland_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
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| D | tonga_ih.c | 86 WREG32(mmIH_RB_WPTR, 0); in tonga_ih_disable_interrupts()
143 WREG32(mmIH_RB_WPTR, 0); in tonga_ih_irq_init()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
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| D | cik_ih.c | 90 WREG32(mmIH_RB_WPTR, 0); in cik_ih_disable_interrupts()
143 WREG32(mmIH_RB_WPTR, 0); in cik_ih_irq_init()
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| D | vega10_ih.c | 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
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| D | navi10_ih.c | 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
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| D | vega20_ih.c | 64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_d.h | 233 #define mmIH_RB_WPTR 0x0F83 macro
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| D | osssys_4_0_1_offset.h | 128 #define mmIH_RB_WPTR … macro
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| D | osssys_4_0_offset.h | 128 #define mmIH_RB_WPTR … macro
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| D | osssys_4_2_0_offset.h | 130 #define mmIH_RB_WPTR … macro
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| D | osssys_5_0_0_offset.h | 128 #define mmIH_RB_WPTR … macro
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| D | oss_2_4_d.h | 46 #define mmIH_RB_WPTR 0xe33 macro
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| D | oss_3_0_1_d.h | 46 #define mmIH_RB_WPTR 0xe33 macro
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| D | oss_3_0_d.h | 46 #define mmIH_RB_WPTR 0xe33 macro
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| D | oss_2_0_d.h | 46 #define mmIH_RB_WPTR 0xf83 macro
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