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Searched refs:REG_FIELD_GET (Results 1 – 25 of 70) sorted by relevance

123

/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c100 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val); in guc_load_done()
101 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, val); in guc_load_done()
197 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
198 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
204 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
205 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode()
210 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
212 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
213 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_mocs.c286 REG_FIELD_GET(L3_SCC_MASK, reg_val), in xelp_lncf_dump()
287 REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val), in xelp_lncf_dump()
293 REG_FIELD_GET(L3_UPPER_IDX_SCC_MASK, reg_val), in xelp_lncf_dump()
294 REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val), in xelp_lncf_dump()
317 REG_FIELD_GET(LE_CACHEABILITY_MASK, reg_val), in xelp_mocs_dump()
318 REG_FIELD_GET(LE_TGT_CACHE_MASK, reg_val), in xelp_mocs_dump()
319 REG_FIELD_GET(LE_LRUM_MASK, reg_val), in xelp_mocs_dump()
322 REG_FIELD_GET(LE_SCC_MASK, reg_val), in xelp_mocs_dump()
323 REG_FIELD_GET(LE_PFM_MASK, reg_val), in xelp_mocs_dump()
325 REG_FIELD_GET(LE_COS_MASK, reg_val), in xelp_mocs_dump()
[all …]
Dxe_pat.c190 u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); in xelp_dump()
221 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat); in xehp_dump()
252 REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat), in xehpc_dump()
253 REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat); in xehpc_dump()
286 REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat), in xelpg_dump()
287 REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat); in xelpg_dump()
346 REG_FIELD_GET(XE2_L3_CLOS, pat), in xe2_dump()
347 REG_FIELD_GET(XE2_L3_POLICY, pat), in xe2_dump()
348 REG_FIELD_GET(XE2_L4_POLICY, pat), in xe2_dump()
349 REG_FIELD_GET(XE2_COH_MODE, pat), in xe2_dump()
[all …]
Dxe_gt_topology.c134 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); in load_l3_bank_mask()
135 u32 bank_val = REG_FIELD_GET(XE2_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
143 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
145 u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4); in load_l3_bank_mask()
154 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
155 u32 bank_val = REG_FIELD_GET(XEHPC_GT_L3_MODE_MASK, fuse3); in load_l3_bank_mask()
164 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, fuse3); in load_l3_bank_mask()
170 u32 mask = REG_FIELD_GET(XELP_GT_L3_MODE_MASK, ~fuse3); in load_l3_bank_mask()
Dxe_gt_clock.c23 base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK, in read_reference_ts_freq()
27 frac_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK, in read_reference_ts_freq()
40 u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, in get_crystal_clock_freq()
78 freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); in xe_gt_clock_init()
Dxe_hwmon.c176 reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val); in xe_hwmon_power_max_read()
180 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); in xe_hwmon_power_max_read()
182 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); in xe_hwmon_power_max_read()
235 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); in xe_hwmon_power_rated_max_read()
300 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); in xe_hwmon_power_max_interval_show()
301 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); in xe_hwmon_power_max_interval_show()
353 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in xe_hwmon_power_max_interval_store()
354 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in xe_hwmon_power_max_interval_store()
477 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in xe_hwmon_power_curr_crit_read()
506 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); in xe_hwmon_get_voltage()
[all …]
Dxe_guc_pc.c341 pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg)); in mtl_update_rpe_value()
360 pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER; in tgl_update_rpe_value()
396 freq = REG_FIELD_GET(MTL_CAGF_MASK, freq); in xe_guc_pc_get_act_freq()
399 freq = REG_FIELD_GET(CAGF_MASK, freq); in xe_guc_pc_get_act_freq()
430 *freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq); in xe_guc_pc_get_cur_freq()
616 gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); in xe_guc_pc_c_status()
619 gt_c_state = REG_FIELD_GET(RCN_MASK, reg); in xe_guc_pc_c_status()
672 pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg)); in mtl_init_fused_rp_values()
674 pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg)); in mtl_init_fused_rp_values()
689 pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER; in tgl_init_fused_rp_values()
[all …]
Dxe_vram.c173 nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg); in get_flat_ccs_offset()
177 offset_lo = REG_FIELD_GET(XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK, reg); in get_flat_ccs_offset()
180 offset_hi = REG_FIELD_GET(XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK, reg); in get_flat_ccs_offset()
192 offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K; in get_flat_ccs_offset()
252 *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G; in tile_vram_size()
253 *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G; in tile_vram_size()
Dxe_guc.c519 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_load_done()
520 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_load_done()
640 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
641 REG_FIELD_GET(GS_UKERNEL_MASK, status)); in guc_wait_ucode()
645 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); in guc_wait_ucode()
646 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); in guc_wait_ucode()
652 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
654 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
655 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
1162 REG_FIELD_GET(GS_BOOTROM_MASK, status)); in xe_guc_print_info()
[all …]
Dxe_gt_mcr.c243 u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_l3bank()
245 u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK, in init_steering_l3bank()
256 u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_l3bank()
268 u32 fuse = REG_FIELD_GET(L3BANK_MASK, in init_steering_l3bank()
278 u32 mask = REG_FIELD_GET(MEML3_EN_MASK, in init_steering_mslice()
382 u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, in init_steering_sqidi_psmi()
Dxe_lrc.c1231 return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2; in instr_dw()
1234 return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2; in instr_dw()
1244 u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header); in dump_mi_command()
1313 u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw); in dump_gfxpipe_command()
1314 u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw); in dump_gfxpipe_command()
1315 u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw); in dump_gfxpipe_command()
1464 u32 opcode = REG_FIELD_GET(GFX_STATE_OPCODE, *dw); in dump_gfx_state_command()
1512 *dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw), in xe_lrc_dump_default()
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_vdsc.c848 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); in intel_dsc_get_pps_config()
849 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); in intel_dsc_get_pps_config()
860 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); in intel_dsc_get_pps_config()
870 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; in intel_dsc_get_pps_config()
871 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
876 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); in intel_dsc_get_pps_config()
877 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); in intel_dsc_get_pps_config()
882 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
883 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); in intel_dsc_get_pps_config()
888 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); in intel_dsc_get_pps_config()
[all …]
Dintel_pmdemand.c400 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
402 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
404 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
406 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
408 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
410 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
414 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
416 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
418 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
486 u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \ in intel_pmdemand_update_params()
Dintel_lvds.c98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); in intel_lvds_port_enabled()
100 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); in intel_lvds_port_enabled()
168 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
169 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
173 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
174 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
177 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
178 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
Dintel_color.c806 entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
807 entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
808 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
855 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | in i9xx_lut_10_pack()
856 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
857 u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) | in i9xx_lut_10_pack()
858 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
859 u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) | in i9xx_lut_10_pack()
860 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
870 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
[all …]
Dintel_vrr.c405 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); in intel_vrr_get_config()
409 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); in intel_vrr_get_config()
428 REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); in intel_vrr_get_config()
430 REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync); in intel_vrr_get_config()
Dintel_bw.c50 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
65 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
66 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
69 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
70 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
189 dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); in mtl_read_qgv_point_info()
191 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
192 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
194 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
195 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
Dintel_hti.c40 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state); in intel_hti_dpll_mask()
Dintel_cx0_phy.c180 if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) { in intel_cx0_wait_for_ack()
226 return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); in __intel_cx0_read_once()
2312 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2316 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2320 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2321 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2322 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2326 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2330 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2331 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
[all …]
Dskl_watermark.c90 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); in intel_sagv_block_time()
785 REG_FIELD_GET(PLANE_BUF_START_MASK, reg), in skl_ddb_entry_init_from_hw()
786 REG_FIELD_GET(PLANE_BUF_END_MASK, reg)); in skl_ddb_entry_init_from_hw()
2919 level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); in skl_wm_level_from_reg_val()
2920 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
3327 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3328 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3331 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3332 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3335 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
[all …]
Dintel_crt.c718 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; in intel_crt_load_detect()
719 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; in intel_crt_load_detect()
721 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; in intel_crt_load_detect()
722 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; in intel_crt_load_detect()
756 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; in intel_crt_load_detect()
Dskl_scaler.c884 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), in skl_scaler_get_config()
885 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), in skl_scaler_get_config()
886 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), in skl_scaler_get_config()
887 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); in skl_scaler_get_config()
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_hwmon.c108 reg_value = REG_FIELD_GET(field_msk, reg_value); in hwm_field_read_and_scale()
178 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); in hwm_power1_max_interval_show()
179 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); in hwm_power1_max_interval_show()
222 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); in hwm_power1_max_interval_store()
223 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); in hwm_power1_max_interval_store()
338 *val = DIV_ROUND_CLOSEST(REG_FIELD_GET(GEN12_VOLTAGE_MASK, reg_value) * 25, 10); in hwm_in_read()
396 min = REG_FIELD_GET(PKG_MIN_PWR, r); in hwm_power_max_read()
398 max = REG_FIELD_GET(PKG_MAX_PWR, r); in hwm_power_max_read()
486 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_power_read()
603 *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), in hwm_curr_read()
[all …]
Dintel_device_info.c303 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); in ip_ver_read()
304 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); in ip_ver_read()
305 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); in ip_ver_read()
/linux-6.12.1/drivers/gpu/drm/i915/soc/
Dintel_dram.c667 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { in xelpdp_get_dram_info()
695 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
696 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()

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