90 		return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);  in intel_sagv_block_time()
785 			   REG_FIELD_GET(PLANE_BUF_START_MASK, reg),  in skl_ddb_entry_init_from_hw()
786 			   REG_FIELD_GET(PLANE_BUF_END_MASK, reg));  in skl_ddb_entry_init_from_hw()
2919 	level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);  in skl_wm_level_from_reg_val()
2920 	level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);  in skl_wm_level_from_reg_val()
3327 	wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);  in mtl_read_wm_latency()
3328 	wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);  in mtl_read_wm_latency()
3331 	wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);  in mtl_read_wm_latency()
3332 	wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);  in mtl_read_wm_latency()
3335 	wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);  in mtl_read_wm_latency()
3336 	wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);  in mtl_read_wm_latency()
3357 	wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;  in skl_read_wm_latency()
3358 	wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;  in skl_read_wm_latency()
3359 	wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;  in skl_read_wm_latency()
3360 	wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;  in skl_read_wm_latency()
3370 	wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;  in skl_read_wm_latency()
3371 	wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;  in skl_read_wm_latency()
3372 	wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;  in skl_read_wm_latency()
3373 	wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;  in skl_read_wm_latency()