Searched refs:MCR_REG (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_regs.h | 365 #define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
368 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
371 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
415 #define XEHP_CULLBIT1 MCR_REG(0x6100)
417 #define CHICKEN_RASTER_2 MCR_REG(0x6208)
420 #define VFLSKPD MCR_REG(0x62a8)
426 #define XEHP_FF_MODE2 MCR_REG(0x6604)
432 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
464 #define XEHP_CULLBIT2 MCR_REG(0x7030)
469 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_ads.c | 421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_reg_defs.h | 273 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) macro
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