Lines Matching refs:MCR_REG
365 #define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
368 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
371 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
415 #define XEHP_CULLBIT1 MCR_REG(0x6100)
417 #define CHICKEN_RASTER_2 MCR_REG(0x6208)
420 #define VFLSKPD MCR_REG(0x62a8)
426 #define XEHP_FF_MODE2 MCR_REG(0x6604)
432 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
464 #define XEHP_CULLBIT2 MCR_REG(0x7030)
469 #define XEHP_PSS_MODE2 MCR_REG(0x703c)
472 #define XEHP_PSS_CHICKEN MCR_REG(0x7044)
494 #define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
501 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
540 #define XEHP_SQCM MCR_REG(0x8724)
727 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
739 #define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
743 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
746 #define SSMCGCTL9530 MCR_REG(0x9530)
749 #define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
960 #define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4)
977 #define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
980 #define GEN8_L3SQCREG1 MCR_REG(0xb100)
991 #define GEN8_L3SQCREG4 MCR_REG(0xb118)
997 #define GEN9_SCRATCH1 MCR_REG(0xb11c)
1000 #define BDW_SCRATCH1 MCR_REG(0xb11c)
1003 #define GEN11_SCRATCH2 MCR_REG(0xb140)
1006 #define XEHP_L3SQCREG5 MCR_REG(0xb158)
1009 #define XEHP_L3SCQREG7 MCR_REG(0xb188)
1034 #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
1036 #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
1041 #define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
1050 #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8)
1052 #define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc)
1054 #define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0)
1056 #define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4)
1058 #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
1061 #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
1062 #define COMP_MOD_CTRL MCR_REG(0xcf30)
1064 #define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
1066 #define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
1070 #define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
1075 #define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
1082 #define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
1089 #define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
1091 #define GEN8_ROW_INSTDONE MCR_REG(0xe164)
1093 #define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
1097 #define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
1103 #define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
1107 #define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
1114 #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
1120 #define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
1135 #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
1144 #define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c)
1148 #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
1159 #define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
1167 #define RT_CTRL MCR_REG(0xe530)
1175 #define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
1179 #define ICL_HDC_MODE MCR_REG(0xe5f4)
1185 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
1188 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
1196 #define SARB_CHICKEN1 MCR_REG(0xe90c)