Searched refs:CM_REV_CM3 (Results 1 – 8 of 8) sorted by relevance
94 if (mips_cm_revision() >= CM_REV_CM3) in mips_cpc_lock_other()115 if (mips_cm_revision() >= CM_REV_CM3) in mips_cpc_unlock_other()
289 mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3); in mips_cm_probe()306 if (cm_rev >= CM_REV_CM3) { in mips_cm_lock_other()359 if (mips_cm_revision() < CM_REV_CM3) { in mips_cm_unlock_other()386 if (revision < CM_REV_CM3) { /* CM2 */ in mips_cm_error_report()
203 if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) in cps_smp_setup()320 if (mips_cm_revision() < CM_REV_CM3) in boot_core()329 if (mips_cm_revision() >= CM_REV_CM3) { in boot_core()456 if (mips_cm_revision() >= CM_REV_CM3) { in cps_init_secondary()
473 if (mips_cm_revision() < CM_REV_CM3) { in cps_gen_entry_code()561 uasm_i_addiu(&p, GPR_T0, GPR_ZERO, mips_cm_revision() < CM_REV_CM3 in cps_gen_entry_code()
1693 if (mips_cm_revision() >= CM_REV_CM3) { in parity_protection_init()
200 if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) in __gic_clocksource_init()264 if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) { in gic_clocksource_of_init()
174 #define CM_REV_CM3 CM_ENCODE_REV(8, 0) macro384 if (mips_cm_revision() >= CM_REV_CM3) in mips_cm_max_vp_width()
192 if (mips_cm_revision() >= CM_REV_CM3) in mips_sc_probe()