| /linux-6.12.1/drivers/staging/media/atomisp/pci/isp/kernels/bnr/bnr2_2/ |
| D | ia_css_bnr2_2_types.h | 63 s32 detail_gain; /** Gain for low contrast texture control */
64 s32 detail_gain_divisor; /** Gain divisor for low contrast texture control */
65 s32 detail_level_offset; /** Bias value for low contrast texture control */
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | radeon_drv.h | 74 * Add texture rectangle support for r100.
86 * 1.15- Add support for texture micro tiling
89 * texture filtering on r200
98 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
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| D | r600_cs.c | 1460 * @texture: texture's bo structure
1467 * the texture and mipmap bo object are big enough to cover this resource.
1470 struct radeon_bo *texture, in r600_check_texture_resource() argument
1546 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); in r600_check_texture_resource()
1550 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in r600_check_texture_resource()
1581 dev_warn(p->dev, "texture blevel %d > llevel %d\n", in r600_check_texture_resource()
1593 /* using get ib will give us the offset into the texture bo */ in r600_check_texture_resource()
1594 if ((l0_size + word2) > radeon_bo_size(texture)) { in r600_check_texture_resource()
1595 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1598 l0_size, radeon_bo_size(texture)); in r600_check_texture_resource()
[all …]
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| D | r300_reg.h | 232 * mode, the swizzling pattern is e.g. used to set zw components in texture
626 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
641 /* Only used for texture coordinates.
642 * Use the source field to route texture coordinate input from the
791 /* BEGIN: Texture specification */
794 * The texture specification dwords are grouped by meaning and not by texture
795 * unit. This means that e.g. the offset for texture image unit N is found in
965 /* END: Texture specification */
970 * There are separate instruction streams for texture instructions and ALU
1029 * As far as I can tell, texture instructions cannot write into output
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| D | evergreen_cs.c | 755 struct radeon_bo *texture, in evergreen_cs_track_validate_texture() argument
794 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
815 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
820 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
829 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
831 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
837 /* check texture size */ in evergreen_cs_track_validate_texture()
839 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
853 if (toffset > radeon_bo_size(texture)) { in evergreen_cs_track_validate_texture()
854 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
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| /linux-6.12.1/drivers/gpu/drm/v3d/ |
| D | v3d_gem.c | 22 /* Set OVRTMUOUT, which means that the texture sampler uniform in v3d_init_core()
24 * using the hardware default behavior based on the texture in v3d_init_core()
26 * "2" in the indirect texture state's output_type field. in v3d_init_core()
162 /* Invalidates texture L2 cachelines */
180 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
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| D | v3d_perfmon.c | 37 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
127 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
130 {"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"},
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| D | v3d_drv.c | 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | renesas,imr.yaml | 15 capture data or data in an external memory as 2D texture data and performing
16 texture mapping and drawing with respect to any shape that is split into
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| /linux-6.12.1/drivers/staging/media/atomisp/pci/isp/kernels/tdf/tdf_1.0/ |
| D | ia_css_tdf_types.h | 38 s32 eps_scale_text; /** Epsilon scaling coefficient for texture region. */
43 s32 blend_text; /** Blending ratio at texture region. */
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| /linux-6.12.1/drivers/char/agp/ |
| D | Kconfig | 14 If you need more texture memory than you can get with the AGP GART
17 and have up to a couple gigs of texture space.
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| /linux-6.12.1/drivers/gpu/drm/vc4/ |
| D | vc4_validate.c | 177 * never have a render target larger than 4096. The texture in vc4_check_tex_size()
675 DRM_DEBUG("Texture format %d unsupported\n", type); in reloc_tex()
695 /* The mipmap levels are stored before the base of the texture. Make in reloc_tex()
748 DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0); in reloc_tex()
749 DRM_INFO("Texture p1 at %d: 0x%08x\n", sample->p_offset[1], p1); in reloc_tex()
750 DRM_INFO("Texture p2 at %d: 0x%08x\n", sample->p_offset[2], p2); in reloc_tex()
751 DRM_INFO("Texture p3 at %d: 0x%08x\n", sample->p_offset[3], p3); in reloc_tex()
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| D | vc4_drv.h | 803 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
806 * This will be used at draw time to relocate the reference to the texture
813 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
814 * Setup") for definitions of the texture parameters.
828 * and validate the shader state record's uniforms that define the texture
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| D | vc4_validate_shaders.c | 31 * (reading it as a texture, uniform data, or direct-addressed TMU
35 * accesses are appropriately bounded, and recording where texture
207 /* Make sure that this texture load is an add of the base in check_tmu_write()
250 "texture setup.\n"); in check_tmu_write()
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| /linux-6.12.1/include/uapi/drm/ |
| D | vc4_drm.h | 112 /* Pointer to uniform data and texture handles for the textures
117 * uniform data has a __u32 index into bo_handles per texture
119 * the program. Following the texture BO handle indices is the actual
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| D | radeon_drm.h | 406 /* Setup registers for each texture unit
680 int width; /* Texture image coordinates */
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| /linux-6.12.1/drivers/gpu/drm/vmwgfx/ |
| D | vmw_surface_cache.h | 333 * @num_layers: Number of slices in an array texture or number of faces in
334 * a cubemap texture.
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| D | vmwgfx_binding.h | 84 * struct vmw_ctx_bindinfo_tex - texture stage binding metadata
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| D | vmwgfx_binding.c | 75 * @texture_units: Texture units bindings.
631 * vmw_binding_scrub_texture - scrub a texture binding from a context.
637 * a list of texture bindings and combines them to a single command.
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_scheduler_types.h | 41 * (e.g. we have to wait until the pixels have been rendering into a texture
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos850-clock.yaml | 269 - description: Image Texture Processing core clock (from CMU_TOP)
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| /linux-6.12.1/Documentation/fb/ |
| D | sisfb.rst | 22 used by DRM/DRI for 3D texture and other data. This memory management is
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv50.c | 94 { 0x0000000a, "TEXTURE" },
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | ctxnv40.c | 350 for (i = 0; i < 16; i++) { /* fragment texture units */ in nv40_gr_construct_state3d()
358 for (i = 0; i < 4; i++) { /* vertex texture units */ in nv40_gr_construct_state3d()
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| D | nv50.c | 347 case 6: /* texture error... unknown for now */ in nv50_gr_tp_trap()
585 /* TEXTURE: CUDA texturing units */ in nv50_gr_trap_handler()
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