Lines Matching full:texture
755 struct radeon_bo *texture, in evergreen_cs_track_validate_texture() argument
794 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
815 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
820 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
829 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
831 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
837 /* check texture size */ in evergreen_cs_track_validate_texture()
839 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
853 if (toffset > radeon_bo_size(texture)) { in evergreen_cs_track_validate_texture()
854 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
858 depth, radeon_bo_size(texture), in evergreen_cs_track_validate_texture()
2349 struct radeon_bo *texture, *mipmap; in evergreen_packet3_check() local
2378 texture = reloc->robj; in evergreen_packet3_check()
2388 /* MIP_ADDRESS should point to FMASK for an MSAA texture. in evergreen_packet3_check()
2402 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()