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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: System Control and Management Interface (SCMI) Message Protocol
11 - Sudeep Holla <sudeep.holla@arm.com>
14 The SCMI is intended to allow agents such as OSPM to manage various functions
19 the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
30 const: scmi
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/linux-6.12.1/drivers/firmware/arm_scmi/transports/
Dsmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * System Control and Management Interface (SCMI) Message SMC/HVC
9 #include <linux/arm-smccc.h>
26 * The shmem address is split into 4K page and offset.
29 * This however limits the shmem address to 44 bit.
32 * scmi instances that are using the same smc-id.
40 #define SHMEM_OFFSET(x) ((x) & (SHMEM_SIZE - 1))
43 * struct scmi_smc - Structure representing a SCMI smc transport
46 * @cinfo: SCMI channel info
47 * @shmem: Transmit/Receive shared memory area
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Doptee.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Linaro Ltd.
24 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
32 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
36 * Shared memory used for SCMI message/response exhange is expected
37 * already identified and bound to channel handle in both SCMI agent
38 * and SCMI server (OP-TEE) parts.
39 * The memory uses SMT header to carry SCMI meta-data (protocol ID and
45 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message
48 * [in/out] memref[1]: Message/response buffer (SMT and SCMI payload)
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Dmailbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * System Control and Management Interface (SCMI) Message Mailbox Transport
6 * Copyright (C) 2019-2024 ARM Ltd.
20 * struct scmi_mailbox - Structure representing a SCMI mailbox transport
23 * @chan: Transmit/Receive mailbox uni/bi-directional channel
26 * @cinfo: SCMI channel info
27 * @shmem: Transmit/Receive shared memory area
36 struct scmi_shared_mem __iomem *shmem; member
48 core->shmem->tx_prepare(smbox->shmem, m, smbox->cinfo); in tx_prepare()
61 * a previous timed-out reply which arrived late could be wrongly in rx_callback()
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/linux-6.12.1/drivers/firmware/arm_scmi/
Dshmem.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2024 ARM Ltd.
20 * SCMI specification requires all parameters, message headers, return
37 static void shmem_tx_prepare(struct scmi_shared_mem __iomem *shmem, in shmem_tx_prepare() argument
47 * overwriting its response with new message payload or vice-versa. in shmem_tx_prepare()
49 * not to bail-out on intermittent issues where the platform is in shmem_tx_prepare()
52 * Note that after a timeout is detected we bail-out and carry on but in shmem_tx_prepare()
55 * due to a misbehaving SCMI firmware. in shmem_tx_prepare()
57 stop = ktime_add_ms(ktime_get(), 2 * cinfo->rx_timeout_ms); in shmem_tx_prepare()
58 spin_until_cond((ioread32(&shmem->channel_status) & in shmem_tx_prepare()
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Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * System Control and Management Interface (SCMI) Message Protocol
5 * and function prototypes used in all the different SCMI protocols.
7 * Copyright (C) 2018-2024 ARM Ltd.
36 SCMI_ERR_SUPPORT = -1, /* Not supported */
37 SCMI_ERR_PARAMS = -2, /* Invalid Parameters */
38 SCMI_ERR_ACCESS = -3, /* Invalid access/permission denied */
39 SCMI_ERR_ENTRY = -4, /* Not found */
40 SCMI_ERR_RANGE = -5, /* Value out of range */
41 SCMI_ERR_BUSY = -6, /* Device busy */
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DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 scmi-bus-y = bus.o
3 scmi-core-objs := $(scmi-bus-y)
5 scmi-driver-y = driver.o notify.o
6 scmi-driver-$(CONFIG_ARM_SCMI_RAW_MODE_SUPPORT) += raw_mode.o
7 scmi-transport-$(CONFIG_ARM_SCMI_HAVE_SHMEM) = shmem.o
8 scmi-transport-$(CONFIG_ARM_SCMI_HAVE_MSG) += msg.o
9 scmi-protocols-y := base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o
10 scmi-protocols-y += pinctrl.o
11 scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y)
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Ddriver.c1 // SPDX-License-Identifier: GPL-2.0
3 * System Control and Management Interface (SCMI) Message Protocol driver
5 * SCMI Message Protocol is used between the System Control Processor(SCP)
7 * provides a mechanism for inter-processor communication between SCP's
14 * Copyright (C) 2018-2024 ARM Ltd.
25 #include <linux/io-64-nonatomic-hi-lo.h>
44 #include <trace/events/scmi.h>
50 /* List of all SCMI devices active in system */
60 * struct scmi_xfers_info - Structure to manage transfer information
68 * a number of xfers equal to the maximum allowed in-flight
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/linux-6.12.1/arch/arm64/boot/dts/arm/
Djuno-scmi.dtsi3 power-domains = <&scmi_devpd 8>;
7 power-domains = <&scmi_devpd 8>;
11 power-domains = <&scmi_devpd 8>;
15 power-domains = <&scmi_devpd 8>;
19 power-domains = <&scmi_devpd 8>;
23 power-domains = <&scmi_devpd 8>;
27 power-domains = <&scmi_devpd 8>;
31 power-domains = <&scmi_devpd 8>;
42 /delete-node/ scpi;
45 scmi {
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/linux-6.12.1/Documentation/devicetree/bindings/mailbox/
Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
31 - const: fsl,imx8-mu-seco
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Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
40 - compatible
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Ds32g2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
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Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
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Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
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Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
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/linux-6.12.1/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
19 Following the generic-names recommended practice, node names should
30 - mmio-sram
31 - amlogic,meson-gxbb-sram
32 - arm,juno-sram-ns
33 - atmel,sama5d2-securam
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/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Damlogic-c3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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