Lines Matching +full:scmi +full:- +full:shmem
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: System Control and Management Interface (SCMI) Message Protocol
11 - Sudeep Holla <sudeep.holla@arm.com>
14 The SCMI is intended to allow agents such as OSPM to manage various functions
19 the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
30 const: scmi
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
41 with shmem address(4KB-page, offset) as parameters
43 - const: arm,scmi-smc-param
44 - description: SCMI compliant firmware with Qualcomm SMC/HVC transport
46 - const: qcom,scmi-smc
47 - description: SCMI compliant firmware with SCMI Virtio transport.
50 - const: arm,scmi-virtio
51 - description: SCMI compliant firmware with OP-TEE transport
53 - const: linaro,scmi-optee
62 interrupt-names:
65 mbox-names:
67 Specifies the mailboxes used to communicate with SCMI compliant
70 - items:
71 - const: tx
72 - const: rx
74 - items:
75 - const: tx
76 - const: tx_reply
77 - const: rx
78 - const: rx_reply
92 while two channel descriptors are needed to represent the SCMI ("tx")
94 The effective combination in numbers of mboxes and shmem descriptors let
95 the SCMI subsystem determine unambiguosly which type of SCMI channels are
97 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel
98 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
99 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
100 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
101 4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels
102 Any other combination of mboxes and shmem is invalid.
106 shmem:
113 '#address-cells':
116 '#size-cells':
119 atomic-threshold-us:
122 platform, the threshold above which any SCMI command, advertised to have
123 an higher-than-threshold execution latency, should not be considered for
127 arm,max-rx-timeout-ms:
131 be a non-zero value if set.
134 arm,smc-id:
139 linaro,optee-channel-id:
142 Channel specifier required when using OP-TEE transport.
145 $ref: '#/$defs/protocol-node'
152 '#power-domain-cells':
156 - '#power-domain-cells'
159 $ref: '#/$defs/protocol-node'
167 $ref: '#/$defs/protocol-node'
174 '#clock-cells':
177 '#power-domain-cells':
181 - required:
182 - '#clock-cells'
184 - required:
185 - '#power-domain-cells'
188 $ref: '#/$defs/protocol-node'
195 '#clock-cells':
199 - '#clock-cells'
202 $ref: '#/$defs/protocol-node'
209 '#thermal-sensor-cells':
213 - '#thermal-sensor-cells'
216 $ref: '#/$defs/protocol-node'
223 '#reset-cells':
227 - '#reset-cells'
230 $ref: '#/$defs/protocol-node'
241 The list of all regulators provided by this SCMI controller.
244 '#address-cells':
247 '#size-cells':
251 '^regulator@[0-9a-f]+$':
262 - reg
265 $ref: '#/$defs/protocol-node'
275 - $ref: '#/$defs/protocol-node'
276 - anyOf:
277 - $ref: /schemas/pinctrl/pinctrl.yaml
278 - $ref: /schemas/firmware/nxp,imx95-scmi-pinctrl.yaml
287 '-pins$':
290 - $ref: /schemas/pinctrl/pincfg-node.yaml#
291 - $ref: /schemas/pinctrl/pinmux-node.yaml#
295 A pin multiplexing sub-node describes how to configure a
297 A single sub-node may define several pin configurations.
298 This sub-node is using the default pinctrl bindings to configure
299 pin multiplexing and using SCMI protocol to apply a specified
303 - reg
308 protocol-node:
311 Each sub-node represents a protocol supported. If the platform
320 mbox-names:
322 - items:
323 - const: tx
324 - const: rx
326 - items:
327 - const: tx
328 - const: tx_reply
329 - const: rx
336 shmem:
340 linaro,optee-channel-id:
343 Channel specifier required when using OP-TEE transport and
347 - reg
350 - compatible
356 const: arm,scmi
360 interrupt-names: false
363 - mboxes
364 - shmem
372 - arm,scmi-smc
373 - arm,scmi-smc-param
374 - qcom,scmi-smc
377 - arm,smc-id
378 - shmem
385 const: linaro,scmi-optee
388 - linaro,optee-channel-id
391 - |
393 scmi {
394 compatible = "arm,scmi";
397 mbox-names = "tx", "rx";
398 shmem = <&cpu_scp_lpri0>,
401 #address-cells = <1>;
402 #size-cells = <0>;
404 atomic-threshold-us = <10000>;
408 #power-domain-cells = <1>;
413 #power-domain-cells = <1>;
417 mbox-names = "tx", "rx";
418 shmem = <&cpu_scp_hpri0>,
424 #clock-cells = <1>;
429 #thermal-sensor-cells = <1>;
434 #reset-cells = <1>;
440 #address-cells = <1>;
441 #size-cells = <0>;
445 regulator-max-microvolt = <3300000>;
450 regulator-min-microvolt = <500000>;
451 regulator-max-microvolt = <4200000>;
463 i2c2-pins {
468 mdio-pins {
470 drive-strength = <24>;
473 keys_pins: keys-pins {
475 bias-pull-up;
482 #address-cells = <2>;
483 #size-cells = <2>;
486 compatible = "mmio-sram";
489 #address-cells = <1>;
490 #size-cells = <1>;
493 cpu_scp_lpri0: scp-sram-section@0 {
494 compatible = "arm,scmi-shmem";
498 cpu_scp_lpri1: scp-sram-section@80 {
499 compatible = "arm,scmi-shmem";
503 cpu_scp_hpri0: scp-sram-section@100 {
504 compatible = "arm,scmi-shmem";
508 cpu_scp_hpri2: scp-sram-section@180 {
509 compatible = "arm,scmi-shmem";
515 - |
517 scmi {
518 compatible = "arm,scmi-smc";
519 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
520 arm,smc-id = <0xc3000001>;
522 #address-cells = <1>;
523 #size-cells = <0>;
527 #power-domain-cells = <1>;
532 - |
534 scmi {
535 compatible = "linaro,scmi-optee";
536 linaro,optee-channel-id = <0>;
538 #address-cells = <1>;
539 #size-cells = <0>;
543 linaro,optee-channel-id = <1>;
544 shmem = <&cpu_optee_lpri0>;
545 #power-domain-cells = <1>;
550 #clock-cells = <1>;
556 #address-cells = <2>;
557 #size-cells = <2>;
560 compatible = "mmio-sram";
563 #address-cells = <1>;
564 #size-cells = <1>;
567 cpu_optee_lpri0: optee-sram-section@0 {
568 compatible = "arm,scmi-shmem";