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/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Damlogic,meson-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - liang.yang@amlogic.com
18 - amlogic,meson-gxl-nfc
19 - amlogic,meson-axg-nfc
24 reg-names:
26 - const: nfc
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Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
35 interesting ways, sometimes with registers that lump multiple NAND-related
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/linux-6.12.1/Documentation/arch/riscv/
Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
12 touching the early boot process. For the purposes of this document, the
13 ``early boot process`` refers to any code that runs before the final virtual
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
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/linux-6.12.1/Documentation/admin-guide/
Dquickly-build-trimmed-linux.rst1 .. SPDX-License-Identifier: (GPL-2.0+ OR CC-BY-4.0)
9 testing purposes, but perfectly fine for day-to-day use, too.
15 section below: it contains a step-by-step guide, which is more detailed, but
20 If your system uses techniques like Secure Boot, prepare it to permit starting
21 self-compiled Linux kernels; install compilers and everything else needed for
26 git clone --depth 1 -b master \
34 make -j $(nproc --all)
37 command -v installkernel && sudo make modules_install install
43 git fetch --depth 1 origin
45 git checkout --force --detach origin/master
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Dverify-bugs-and-bisect-regressions.rst1 .. SPDX-License-Identifier: (GPL-2.0+ OR CC-BY-4.0)
9 currently supported by developers -- to then explain how to locate the change
22 read and navigate this document -- especially when you want to look something
26 https://docs.kernel.org/admin-guide/verify-bugs-and-bisect-regressions.html
32 over to the* ':ref:`step-by-step guide <introguide_bissbs>`' *below. It utilizes
45 *segment 2*. Then you can submit a preliminary report -- or continue with
47 full-fledged regression report. In the following example 6.0.13 is assumed to be
55 # * Ensure Secure Boot permits booting self-compiled Linux kernels.
59 git clone -o mainline --no-checkout \
62 git remote add -t master stable \
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Dbug-bisect.rst1 .. SPDX-License-Identifier: (GPL-2.0+ OR CC-BY-4.0)
9 change that broke something -- for example when some functionality stopped
13 kernel, better follow Documentation/admin-guide/verify-bugs-and-bisect-regressions.rst
17 care about the result -- for example, because the problem happens after the
28 use as pristine base at each bisection step; ideally, you have also worked out
29 a fully reliable and straight-forward way to reproduce the regression, too.*
38 Instead of Git tags like 'v6.0' and 'v6.1' you can specify commit-ids, too.
46 2. Now build, install, and boot a kernel. This might fail for unrelated reasons,
49 go back to step 1.
68 test after this (roughly 10 steps)'. In that case go back to step 1.
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/linux-6.12.1/arch/powerpc/mm/book3s64/
Dhash_pgtable.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
33 * constant relationship between address of struct page and its PFN.
35 * During boot or memory hotplug operation when a new memory section is
41 * ----------------------------------------------
43 * ----------------------------------------------
46 * vmemmap +--------------+ +--------------+
47 * + | page struct | +--------------> | page struct |
48 * | +--------------+ +--------------+
49 * | | page struct | +--------------> | page struct |
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Dhash_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
41 #include <linux/elf-randomize.h>
48 #include <asm/page.h>
60 #include <asm/code-patching.h>
66 #include <asm/pte-walk.h>
67 #include <asm/asm-prototypes.h>
92 * Note: pte --> Linux PTE
93 * HPTE --> PowerPC Hashed Page Table Entry
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/linux-6.12.1/Documentation/firmware-guide/acpi/apei/
Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
11 for early boot messages similar to this one::
15 which shows that the BIOS is exposing an EINJ table - it is the
43 - available_error_type
51 0x00000002 Processor Uncorrectable non-fatal
54 0x00000010 Memory Uncorrectable non-fatal
57 0x00000080 PCI Express Uncorrectable non-fatal
60 0x00000400 Platform Uncorrectable non-fatal
67 - error_type
72 - error_inject
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/linux-6.12.1/arch/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
22 # IOMMUs not handled by dma-iommu. Drivers must never select this symbol.
29 menu "General architecture-dependent options"
34 Select if the architecture can check permissions at sub-page
80 for kernel debugging, non-intrusive instrumentation and testing.
89 makes certain almost-always-true or almost-always-false branch
92 Certain performance-sensitive kernel code, such as trace points,
106 ( On 32-bit x86, the necessary options added to the compiler
113 Boot time self-test of the branch patching code.
119 Boot time self-test of the call patching code.
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/linux-6.12.1/Documentation/arch/x86/
Dpat.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PAT (Page Attribute Table)
7 x86 Page Attribute Table (PAT) allows for setting the memory attribute at the
8 page level granularity. PAT is complementary to the MTRR settings which allows
10 more flexible than MTRR due to its capability to set attributes at page level
20 WB Write-back
22 WC Write-combined
23 WT Write-through
24 UC- Uncached Minus
32 attributes at the page level. In order to avoid aliasing, these interfaces
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Dtdx.rst1 .. SPDX-License-Identifier: GPL-2.0
18 CPU-attested software module called 'the TDX module' runs inside the new
22 TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to
23 provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs
32 TDX boot-time detection
33 -----------------------
36 boot. Below dmesg shows when TDX is enabled by BIOS::
41 ---------------------------------------
59 Besides initializing the TDX module, a per-cpu initialization SEAMCALL
103 ------------------------------------------
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Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Linux/x86 Boot Protocol
7 On the x86 platform, the Linux kernel uses a rather complicated boot
12 real-mode DOS as a mainstream operating system.
14 Currently, the following versions of the Linux/x86 boot protocol exist.
22 boot loader and the kernel. setup.S made relocatable,
28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
31 safe for systems which use the EBDA from SMM or 32-bit
35 Protocol 2.03 (Kernel 2.4.18-pre1) Explicitly makes the highest possible
44 the boot command line.
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Dsgx.rst1 .. SPDX-License-Identifier: GPL-2.0
13 * Privileged (ring-0) ENCLS functions orchestrate the construction of the
15 * Unprivileged (ring-3) ENCLU functions allow an application to enter and
34 Enclave Page Cache
37 SGX utilizes an *Enclave Page Cache (EPC)* to store pages that are associated
38 with an enclave. It is contained in a BIOS-reserved region of physical memory.
48 Enclave Page Types
49 ------------------
64 number for a page evicted from the EPC.
66 Enclave Page Cache Map
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/linux-6.12.1/arch/x86/include/asm/
Dx86_init.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct x86_init_mpparse - platform specific mpparse ops
28 * struct x86_init_resources - platform specific resource related ops
43 * struct x86_init_irqs - platform specific interrupt setup
60 * struct x86_init_oem - oem platform specific customizing functions
70 * struct x86_init_paging - platform specific paging functions
81 * struct x86_init_timers - platform specific timer setup
83 * boot cpu
94 * struct x86_init_iommu - platform specific iommu setup
102 * struct x86_init_pci - platform specific pci init functions
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/linux-6.12.1/arch/xtensa/kernel/
Dhead.S10 * Copyright (C) 2001 - 2008 Tensilica Inc.
20 #include <asm/page.h>
34 * - The kernel image has been loaded to the actual address where it was
36 * - a2 contains either 0 or a pointer to a list of boot parameters.
44 * The bootloader passes a pointer to a list of boot parameters in a2.
53 .begin no-absolute-literals
57 /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
67 * xt-gdb to single step via DEBUG exceptions received directly
84 Offset = _SetupMMU - _start
106 .end no-absolute-literals
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/linux-6.12.1/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
68 /* Extended commands for large page devices */
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
97 * Enable generic NAND 'page erased' check. This check is only done when
98 * ecc.correct() returns -EBADMSG.
120 /* Options valid for Samsung large page devices */
124 * Chip requires ready check on read (for auto-incremented sequential read).
125 * True only for small page devices; large page devices do not support
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/linux-6.12.1/drivers/mtd/nand/raw/
Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
173 * the driver calls the chunks 'step' or 'codeword' interchangeably
178 * the largest page size we support is 8K, this will have 16 steps/codewords
207 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
210 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
214 ((chip)->reg_read_dma + \
215 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
244 * @bam_ce - the array of BAM command elements
245 * @cmd_sgl - sgl for NAND BAM command pipe
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/linux-6.12.1/arch/arm64/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
272 ARM 64-bit (AArch64) Linux support.
280 # required due to use of the -Zfixed-x18 flag.
283 # -Zsanitizer=shadow-call-stack flag.
293 depends on $(cc-option,-fpatchable-function-entry=2)
319 # VA_BITS - PAGE_SHIFT - 3
397 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
402 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
452 at stage-2.
460 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
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/linux-6.12.1/arch/x86/kernel/
Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
18 #include <asm/page.h>
21 #include <asm/processor-flags.h>
25 #include <asm/nospec-branch.h>
32 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
33 * because we need identity-mapped pages.
42 * and someone has loaded an identity mapped page table
43 * for us. These identity mapped page tables map all of the
51 * arch/x86/boot/compressed/head_64.S.
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/linux-6.12.1/Documentation/filesystems/
Dramfs-rootfs-initramfs.rst1 .. SPDX-License-Identifier: GPL-2.0
12 --------------
15 mechanisms (the page cache and dentry cache) as a dynamically resizable
16 RAM-based filesystem.
28 dentries and page cache as usual, but there's nowhere to write them to.
39 ------------------
45 fake block device into the page cache (and copying changes back out), as well
51 to avoid this copying by playing with the page tables, but they're unpleasantly
54 since all file access goes through the page and dentry caches. The RAM
57 Another reason ramdisks are semi-obsolete is that the introduction of
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/linux-6.12.1/arch/arm64/kernel/
Dhibernate.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Ubuntu project, hibernation support for mach-dove
50 /* hyp-stub vectors, used to restore el2 during resume from hibernate. */
54 * The logical cpu number we should resume on, initialised to a non-cpu
57 static int sleep_cpu = -EINVAL;
78 * re-configure el2.
88 memcpy(i->uts_version, init_utsname()->version, sizeof(i->uts_version)); in arch_hdr_invariants()
94 unsigned long nosave_end_pfn = sym_to_pfn(&__nosave_end - 1); in pfn_is_nosave()
113 return -EOVERFLOW; in arch_hibernation_header_save()
115 arch_hdr_invariants(&hdr->invariants); in arch_hibernation_header_save()
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/linux-6.12.1/Documentation/core-api/
Ddma-isa-lpc.rst12 ------------------------
16 #include <linux/dma-mapping.h>
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
28 -----------------
37 The DMA-able address space is the lowest 16 MB of _physical_ memory.
38 Also the transfer block may not cross page boundaries (which are 64
45 allocate the memory during boot-up it's a good idea to also pass
52 -------------------
66 --------
69 8-bit transfers and the upper four are for 16-bit transfers.
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/linux-6.12.1/arch/arm64/boot/dts/broadcom/northstar2/
Dns2-svk.dts33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
117 pl022,slave-tx-disable = <0>;
118 pl022,com-mode = <0>;
119 pl022,rx-level-trig = <1>;
120 pl022,tx-level-trig = <1>;
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/linux-6.12.1/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
68 * the next hard reset. This case occurs in the NAND boot mode. When the board
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
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