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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dnxp,lpc1850-wwdt.yaml48 reg = <0x40080000 0x24>;
/linux-6.12.1/arch/sh/drivers/pci/
Dfixups-rts7751r2d.c17 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
18 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
48 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM); in pci_fixup_pcic()
49 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM); in pci_fixup_pcic()
51 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); in pci_fixup_pcic()
58 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
59 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
60 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
[all …]
Dfixups-landisk.c18 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
19 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
29 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq()
31 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq()
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
51 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
53 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
54 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic()
56 return 0; in pci_fixup_pcic()
Dfixups-se7751.c14 case 0: return evt2irq(0x3a0); in pcibios_map_platform_irq()
15 case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */ in pcibios_map_platform_irq()
25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
58 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ in pci_fixup_pcic()
61 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); in pci_fixup_pcic()
73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); in pci_fixup_pcic()
76 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ in pci_fixup_pcic()
77 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ in pci_fixup_pcic()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Ds32v234.dtsi9 /memreserve/ 0x80000000 0x00010000;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0x0 0x0>;
31 cpu-release-addr = <0x0 0x80000000>;
38 reg = <0x0 0x1>;
40 cpu-release-addr = <0x0 0x80000000>;
47 reg = <0x0 0x100>;
49 cpu-release-addr = <0x0 0x80000000>;
56 reg = <0x0 0x101>;
[all …]
/linux-6.12.1/drivers/net/wireless/rsi/
Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml50 cell 0: index of dma channel mux instance.
54 cell 0: peripheral dma request id.
186 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
234 reg = <0x40018000 0x2000>,
235 <0x40024000 0x1000>,
236 <0x40025000 0x1000>;
237 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
238 <0 9 IRQ_TYPE_LEVEL_HIGH>;
252 reg = <0x40080000 0x2000>,
253 <0x40210000 0x1000>;
[all …]
/linux-6.12.1/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi38 #size-cells = <0>;
43 reg = <0xf00>;
51 reg = <0x40021000 0x1000>,
52 <0x40022000 0x1000>;
59 #clock-cells = <0>;
66 #clock-cells = <0>;
73 #clock-cells = <0>;
80 #clock-cells = <0>;
87 #clock-cells = <0>;
94 reg = <0x40000000 0x800000>;
[all …]
/linux-6.12.1/arch/arm/mach-lpc32xx/
Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvfxxx.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 offset = <0x0>;
47 mask = <0x1000>;
66 reg = <0x40000000 0x00070000>;
71 reg = <0x40001000 0x800>;
76 reg = <0x40001800 0x400>;
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra210.c33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
43 #define PLLC_OUT 0x84
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]