Lines Matching +full:0 +full:x40080000

45 #define FLASH_SIZE_ADDR			0x04000016
46 #define PING_BUFFER_ADDRESS		0x19000
47 #define PONG_BUFFER_ADDRESS		0x1a000
48 #define SWBL_REGIN			0x41050034
49 #define SWBL_REGOUT			0x4105003c
50 #define PING_WRITE			0x1
51 #define PONG_WRITE			0x2
56 #define REGIN_VALID			0xA
57 #define REGIN_INPUT			0xA0
58 #define REGOUT_VALID			0xAB
59 #define REGOUT_INVALID			(~0xAB)
60 #define CMD_PASS			0xAA
61 #define CMD_FAIL			0xCC
77 #define RSI_ULP_RESET_REG		0x161
78 #define RSI_WATCH_DOG_TIMER_1		0x16c
79 #define RSI_WATCH_DOG_TIMER_2		0x16d
80 #define RSI_WATCH_DOG_DELAY_TIMER_1		0x16e
81 #define RSI_WATCH_DOG_DELAY_TIMER_2		0x16f
82 #define RSI_WATCH_DOG_TIMER_ENABLE		0x170
85 #define NWP_AHB_BASE_ADDR		0x41300000
86 #define NWP_WWD_INTERRUPT_TIMER		(NWP_AHB_BASE_ADDR + 0x300)
87 #define NWP_WWD_SYSTEM_RESET_TIMER	(NWP_AHB_BASE_ADDR + 0x304)
88 #define NWP_WWD_WINDOW_TIMER		(NWP_AHB_BASE_ADDR + 0x308)
89 #define NWP_WWD_TIMER_SETTINGS		(NWP_AHB_BASE_ADDR + 0x30C)
90 #define NWP_WWD_MODE_AND_RSTART		(NWP_AHB_BASE_ADDR + 0x310)
91 #define NWP_WWD_RESET_BYPASS		(NWP_AHB_BASE_ADDR + 0x314)
92 #define NWP_FSM_INTR_MASK_REG		(NWP_AHB_BASE_ADDR + 0x104)
97 #define NWP_WWD_TIMER_DISABLE		0xAA0001
106 #define RSI_ULP_TIMER_ENABLE		((0xaa000) | RSI_RESTART_WDT |	\
108 #define RSI_RF_SPI_PROG_REG_BASE_ADDR	0x40080000
111 #define RSI_GSPI_CTRL_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
112 #define RSI_GSPI_DATA_REG0		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
113 #define RSI_GSPI_DATA_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
114 #define RSI_GSPI_DATA_REG2		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
116 #define RSI_GSPI_CTRL_REG0_VALUE		0x340
132 #define COMMON_HAL_CARD_READY_IND	0x0
139 #define BBP_INFO_40MHZ 0x6
141 #define FW_FLASH_OFFSET			0x820
142 #define LMAC_VER_OFFSET_9113		(FW_FLASH_OFFSET + 0x200)
143 #define LMAC_VER_OFFSET_9116		0x22C2
148 #define RSI_9116_FW_MAGIC_WORD		0x5aa5
150 #define MEM_ACCESS_CTRL_FROM_HOST	0x41300000
168 #define RSI_BL_CTRL_LEN_MASK			0xFFFFFF