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/linux-6.12.1/sound/pci/aw2/
Dsaa7146.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Jean-Christian Hassler <jhassler@free.fr>
46 #define ME (1UL << 11)
47 #define LIMIT (1UL << 4)
48 #define PV (1UL << 3)
51 #define PPEF (1UL << 31)
52 #define PABO (1UL << 30)
53 #define IIC_S (1UL << 17)
54 #define IIC_E (1UL << 16)
55 #define A2_in (1UL << 15)
[all …]
Daw2-tsl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Jean-Christian Hassler <jhassler@free.fr>
6 * Copyright 1998 Emagic Soft- und Hardware GmbH
13 #define TSL_WS0 (1UL << 31)
14 #define TSL_WS1 (1UL << 30)
15 #define TSL_WS2 (1UL << 29)
16 #define TSL_WS3 (1UL << 28)
17 #define TSL_WS4 (1UL << 27)
18 #define TSL_DIS_A1 (1UL << 24)
19 #define TSL_SDW_A1 (1UL << 23)
[all …]
/linux-6.12.1/arch/sparc/include/asm/
Dchafsr.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * ch --> cheetah
10 * ch+ --> cheetah plus
11 * jp --> jalapeno
15 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only.
19 * signalled at %tl >= 1.
21 #define CHAFSR_TL1 (1UL << 63UL) /* n/a */
26 #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
31 #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
33 /* Hardware corrected E-cache Tag ECC error */
[all …]
Dsfafsr.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define SFAFSR_ME (_AC(1,UL) << SFAFSR_ME_SHIFT)
11 #define SFAFSR_PRIV (_AC(1,UL) << SFAFSR_PRIV_SHIFT)
13 #define SFAFSR_ISAP (_AC(1,UL) << SFAFSR_ISAP_SHIFT)
15 #define SFAFSR_ETP (_AC(1,UL) << SFAFSR_ETP_SHIFT)
17 #define SFAFSR_IVUE (_AC(1,UL) << SFAFSR_IVUE_SHIFT)
19 #define SFAFSR_TO (_AC(1,UL) << SFAFSR_TO_SHIFT)
21 #define SFAFSR_BERR (_AC(1,UL) << SFAFSR_BERR_SHIFT)
23 #define SFAFSR_LDP (_AC(1,UL) << SFAFSR_LDP_SHIFT)
25 #define SFAFSR_CP (_AC(1,UL) << SFAFSR_CP_SHIFT)
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Dpgtable_64.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #include <asm-generic/pgtable-nop4d.h>
26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
32 * Since modules need to be in the lowest 32-bits of the address space,
37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL)
38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
40 #define MODULES_VADDR _AC(0x0000000010000000,UL)
41 #define MODULES_LEN _AC(0x00000000e0000000,UL)
42 #define MODULES_END _AC(0x00000000f0000000,UL)
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Desr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - ARM Ltd
13 #define ESR_ELx_EC_UNKNOWN UL(0x00)
14 #define ESR_ELx_EC_WFx UL(0x01)
16 #define ESR_ELx_EC_CP15_32 UL(0x03)
17 #define ESR_ELx_EC_CP15_64 UL(0x04)
18 #define ESR_ELx_EC_CP14_MR UL(0x05)
19 #define ESR_ELx_EC_CP14_LS UL(0x06)
20 #define ESR_ELx_EC_FP_ASIMD UL(0x07)
21 #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
[all …]
Dpgtable-hwdef.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * Number of page-table levels required to address 'va_bits' wide
12 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
13 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
15 * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
17 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
22 * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
26 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
29 * Size mapped by an entry at level n ( -1 <= n <= 3)
30 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
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Dkvm_arm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
17 #define HCR_TID5 (UL(1) << 58)
18 #define HCR_DCT (UL(1) << 57)
20 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
21 #define HCR_TTLBOS (UL(1) << 55)
22 #define HCR_TTLBIS (UL(1) << 54)
23 #define HCR_ENSCXT (UL(1) << 53)
24 #define HCR_TOCU (UL(1) << 52)
25 #define HCR_AMVOFFEN (UL(1) << 51)
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/linux-6.12.1/arch/arm64/include/uapi/asm/
Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
21 * HWCAP flags - for AT_HWCAP
24 * Bits 32-61 are unallocated for potential use by libc.
26 #define HWCAP_FP (1 << 0)
27 #define HWCAP_ASIMD (1 << 1)
28 #define HWCAP_EVTSTRM (1 << 2)
29 #define HWCAP_AES (1 << 3)
30 #define HWCAP_PMULL (1 << 4)
31 #define HWCAP_SHA1 (1 << 5)
32 #define HWCAP_SHA2 (1 << 6)
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/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra124-dfll-fcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
21 #include "clk-dfll.h"
33 [0] = 2014500000UL,
34 [1] = 2320500000UL,
35 [2] = 2116500000UL,
36 [3] = 2524500000UL,
41 .speedo_id = -1,
42 .process_id = -1,
48 { 204000000UL, { 1112619, -29295, 402 } },
[all …]
/linux-6.12.1/lib/
Dpercpu_test.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * +ul_one/-ul_one below would replace with inc/dec instructions. in percpu_test_init()
26 volatile unsigned int ui_one = 1; in percpu_test_init()
28 unsigned long ul = 0; in percpu_test_init() local
34 l += -1; in percpu_test_init()
35 __this_cpu_add(long_counter, -1); in percpu_test_init()
36 CHECK(l, long_counter, -1); in percpu_test_init()
38 l += 1; in percpu_test_init()
39 __this_cpu_add(long_counter, 1); in percpu_test_init()
42 ul = 0; in percpu_test_init()
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/linux-6.12.1/arch/alpha/include/uapi/asm/
Dfpu.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 * Alpha floating-point control register defines:
9 #define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */
10 #define FPCR_DNZ (1UL<<48) /* denorms to zero */
11 #define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */
12 #define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */
13 #define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */
14 #define FPCR_INV (1UL<<52) /* invalid operation */
15 #define FPCR_DZE (1UL<<53) /* division by zero */
16 #define FPCR_OVF (1UL<<54) /* overflow */
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/linux-6.12.1/arch/riscv/include/asm/
Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
[all …]
/linux-6.12.1/tools/arch/riscv/include/asm/
Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
13 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
14 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
15 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
17 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
18 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
20 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
21 #define SR_FS_OFF _AC(0x00000000, UL)
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/linux-6.12.1/arch/s390/include/uapi/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
96 #define PT_ENDREGS 0x140-1
162 #define PT_ENDREGS 0x1B0-1
173 #define PSW_MASK_PER _AC(0x40000000, UL)
174 #define PSW_MASK_DAT _AC(0x04000000, UL)
175 #define PSW_MASK_IO _AC(0x02000000, UL)
176 #define PSW_MASK_EXT _AC(0x01000000, UL)
177 #define PSW_MASK_KEY _AC(0x00F00000, UL)
178 #define PSW_MASK_BASE _AC(0x00080000, UL) /* always one */
179 #define PSW_MASK_MCHECK _AC(0x00040000, UL)
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/linux-6.12.1/include/uapi/rdma/hfi/
Dhfi1_user.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
9 * Copyright(c) 2015 - 2020 Intel Corporation.
28 * - Redistributions of source code must retain the above copyright
30 * - Redistributions in binary form must reproduce the above copyright
34 * - Neither the name of Intel Corporation nor the names of its
93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
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/linux-6.12.1/include/linux/sunrpc/
Dgss_err.h4 * Adapted from MIT Kerberos 5-1.2.1 include/gssapi/gssapi.h
40 * Flag bits for context-level services.
42 #define GSS_C_DELEG_FLAG 1
56 #define GSS_C_INITIATE 1
62 #define GSS_C_GSS_CODE 1
67 * Expiration time of 2^32-1 seconds means infinite lifetime for a
83 #define GSS_C_CALLING_ERROR_MASK ((OM_uint32) 0377ul)
84 #define GSS_C_ROUTINE_ERROR_MASK ((OM_uint32) 0377ul)
85 #define GSS_C_SUPPLEMENTARY_MASK ((OM_uint32) 0177777ul)
110 (((OM_uint32) 1ul) << GSS_C_CALLING_ERROR_OFFSET)
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/linux-6.12.1/arch/alpha/include/asm/
Dwrperfmon.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define PERFMON_CMD_ENABLE 1
28 #define EV5_PCTR_0 (1UL<<0)
29 #define EV5_PCTR_1 (1UL<<1)
30 #define EV5_PCTR_2 (1UL<<2)
41 #define EV6_PCTR_0 (1UL<<0)
42 #define EV6_PCTR_1 (1UL<<1)
51 #define EV67_PCTR_0 (1UL<<0)
52 #define EV67_PCTR_1 (1UL<<1)
63 * in Table E-23 regarding the bits that set the event PCTR 1 counts.
[all …]
/linux-6.12.1/include/uapi/linux/misc/
Dbcm_vk.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright 2018-2020 Broadcom.
16 #define VK_IMAGE_TYPE_BOOT1 1 /* 1st stage (load to SRAM) */
40 #define VK_FWSTS_RELOCATION_ENTRY (1UL << 0)
41 #define VK_FWSTS_RELOCATION_EXIT (1UL << 1)
42 #define VK_FWSTS_INIT_START (1UL << 2)
43 #define VK_FWSTS_ARCH_INIT_DONE (1UL << 3)
44 #define VK_FWSTS_PRE_KNL1_INIT_DONE (1UL << 4)
45 #define VK_FWSTS_PRE_KNL2_INIT_DONE (1UL << 5)
46 #define VK_FWSTS_POST_KNL_INIT_DONE (1UL << 6)
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/linux-6.12.1/arch/alpha/kernel/
Derr_marvel.c1 // SPDX-License-Identifier: GPL-2.0
49 env = lf_subpackets->env[ev7_lf_env_index(ev_packets[i].type)]; in marvel_print_680_frame()
56 env->cabinet, in marvel_print_680_frame()
57 env->drawer); in marvel_print_680_frame()
58 printk("%s Module Type: 0x%x - Unit ID 0x%x - " in marvel_print_680_frame()
61 env->module_type, in marvel_print_680_frame()
62 env->unit_id, in marvel_print_680_frame()
63 env->condition); in marvel_print_680_frame()
77 if (lf_subpackets->env[i]) in marvel_process_680_frame()
95 "1 cycle (1 or 2 flit packet)", in marvel_print_err_cyc()
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/linux-6.12.1/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 #define IDR0_ST_LVL_2LVL 1
30 #define IDR0_CD2L (1 << 19)
31 #define IDR0_VMID16 (1 << 18)
32 #define IDR0_PRI (1 << 16)
33 #define IDR0_SEV (1 << 14)
34 #define IDR0_MSI (1 << 13)
35 #define IDR0_ASID16 (1 << 12)
36 #define IDR0_ATS (1 << 10)
37 #define IDR0_HYP (1 << 9)
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/linux-6.12.1/arch/sparc/kernel/
Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
61 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
62 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
63 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
65 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
[all …]
Dsbus.c1 // SPDX-License-Identifier: GPL-2.0
37 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
38 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
39 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
40 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
41 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
42 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
43 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
44 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
46 #define IOMMU_DRAM_VALID (1UL << 30UL)
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/linux-6.12.1/arch/s390/include/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PIF_EXECVE_PGSTE_RESTART 1 /* restart execve for PGSTE binaries */
24 #define PSW32_MASK_PER _AC(0x40000000, UL)
25 #define PSW32_MASK_DAT _AC(0x04000000, UL)
26 #define PSW32_MASK_IO _AC(0x02000000, UL)
27 #define PSW32_MASK_EXT _AC(0x01000000, UL)
28 #define PSW32_MASK_KEY _AC(0x00F00000, UL)
29 #define PSW32_MASK_BASE _AC(0x00080000, UL) /* Always one */
30 #define PSW32_MASK_MCHECK _AC(0x00040000, UL)
31 #define PSW32_MASK_WAIT _AC(0x00020000, UL)
[all …]
/linux-6.12.1/include/linux/sched/
Djobctl.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * task->jobctl flags
27 #define JOBCTL_STOP_DEQUEUED (1UL << JOBCTL_STOP_DEQUEUED_BIT)
28 #define JOBCTL_STOP_PENDING (1UL << JOBCTL_STOP_PENDING_BIT)
29 #define JOBCTL_STOP_CONSUME (1UL << JOBCTL_STOP_CONSUME_BIT)
30 #define JOBCTL_TRAP_STOP (1UL << JOBCTL_TRAP_STOP_BIT)
31 #define JOBCTL_TRAP_NOTIFY (1UL << JOBCTL_TRAP_NOTIFY_BIT)
32 #define JOBCTL_TRAPPING (1UL << JOBCTL_TRAPPING_BIT)
33 #define JOBCTL_LISTENING (1UL << JOBCTL_LISTENING_BIT)
34 #define JOBCTL_TRAP_FREEZE (1UL << JOBCTL_TRAP_FREEZE_BIT)
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