include/asm/chafsr.h

1 /* SPDX-License-Identifier: GPL-2.0 */
9  * ch	-->	cheetah
10  * ch+	-->	cheetah plus
11  * jp	-->	jalapeno
15  * read, write 1 to clear.  M_SYNDROME and E_SYNDROME are read-only.
19  * signalled at %tl >= 1.
21 #define CHAFSR_TL1		(1UL << 63UL) /* n/a */
26 #define CHPAFSR_DTO		(1UL << 59UL) /* ch+ */
31 #define CHPAFSR_DBERR		(1UL << 58UL) /* ch+ */
33 /* Hardware corrected E-cache Tag ECC error */
34 #define CHPAFSR_THCE		(1UL << 57UL) /* ch+ */
36 #define JPAFSR_JETO		(1UL << 57UL) /* jp */
38 /* SW handled correctable E-cache Tag ECC error */
39 #define CHPAFSR_TSCE		(1UL << 56UL) /* ch+ */
41 #define JPAFSR_SCE		(1UL << 56UL) /* jp */
43 /* Uncorrectable E-cache Tag ECC error */
44 #define CHPAFSR_TUE		(1UL << 55UL) /* ch+ */
46 #define JPAFSR_JEIC		(1UL << 55UL) /* jp */
51 #define CHPAFSR_DUE		(1UL << 54UL) /* ch+ */
53 #define JPAFSR_JEIT		(1UL << 54UL) /* jp */
65  * 64-byte system bus transaction.  Only the first ECC error in a 16-byte
66  * subunit will be logged.  All errors in subsequent 16-byte subunits
67  * from the same 64-byte transaction are ignored.
69 #define CHAFSR_ME		(1UL << 53UL) /* ch,ch+,jp */
74 #define CHAFSR_PRIV		(1UL << 52UL) /* ch,ch+,jp */
85 #define CHAFSR_PERR		(1UL << 51UL) /* ch,ch+,jp */
91 #define CHAFSR_IERR		(1UL << 50UL) /* ch,ch+,jp */
94 #define CHAFSR_ISAP		(1UL << 49UL) /* ch,ch+,jp */
97 #define CHAFSR_EMC		(1UL << 48UL) /* ch,ch+ */
99 #define JPAFSR_ETP		(1UL << 48UL) /* jp */
102 #define CHAFSR_EMU		(1UL << 47UL) /* ch,ch+ */
104 #define JPAFSR_OM		(1UL << 47UL) /* jp */
107 #define CHAFSR_IVC		(1UL << 46UL) /* ch,ch+ */
109 #define JPAFSR_UMS		(1UL << 46UL) /* jp */
112 #define CHAFSR_IVU		(1UL << 45UL) /* ch,ch+,jp */
115 #define CHAFSR_TO		(1UL << 44UL) /* ch,ch+,jp */
118 #define CHAFSR_BERR		(1UL << 43UL) /* ch,ch+,jp */
120 /* SW Correctable E-cache ECC error for instruction fetch or data access
123 #define CHAFSR_UCC		(1UL << 42UL) /* ch,ch+,jp */
125 /* Uncorrectable E-cache ECC error for instruction fetch or data access
128 #define CHAFSR_UCU		(1UL << 41UL) /* ch,ch+,jp */
131 #define CHAFSR_CPC		(1UL << 40UL) /* ch,ch+,jp */
134 #define CHAFSR_CPU		(1UL << 39UL) /* ch,ch+,jp */
136 /* HW Corrected ECC error from E-cache for writeback */
137 #define CHAFSR_WDC		(1UL << 38UL) /* ch,ch+,jp */
139 /* Uncorrectable ECC error from E-cache for writeback */
140 #define CHAFSR_WDU		(1UL << 37UL) /* ch,ch+,jp */
142 /* HW Corrected ECC error from E-cache for store merge or block load */
143 #define CHAFSR_EDC		(1UL << 36UL) /* ch,ch+,jp */
145 /* Uncorrectable ECC error from E-cache for store merge or block load */
146 #define CHAFSR_EDU		(1UL << 35UL) /* ch,ch+,jp */
149 #define CHAFSR_UE		(1UL << 34UL) /* ch,ch+,jp */
152 #define CHAFSR_CE		(1UL << 33UL) /* ch,ch+,jp */
155 #define JPAFSR_RUE		(1UL << 32UL) /* jp */
158 #define JPAFSR_RCE		(1UL << 31UL) /* jp */
161 #define JPAFSR_BP		(1UL << 30UL) /* jp */
164 #define JPAFSR_WBP		(1UL << 29UL) /* jp */
167 #define JPAFSR_FRC		(1UL << 28UL) /* jp */
170 #define JPAFSR_FRU		(1UL << 27UL) /* jp */
196 #define JPAFSR_JBREQ		(0x7UL << 24UL) /* jp */
197 #define JPAFSR_JBREQ_SHIFT	24UL
200 #define JPAFSR_ETW		(0x3UL << 22UL) /* jp */
201 #define JPAFSR_ETW_SHIFT	22UL
204  * first occurrence of the highest-priority error according to the M_SYND
209 #define CHAFSR_M_SYNDROME	(0xfUL << 16UL) /* ch,ch+,jp */
210 #define CHAFSR_M_SYNDROME_SHIFT	16UL
213 #define JPAFSR_AID		(0x1fUL << 9UL) /* jp */
214 #define JPAFSR_AID_SHIFT	9UL
216 /* System bus or E-cache data ECC syndrome.  This field captures the status
217  * of the first occurrence of the highest-priority error according to the
222 #define CHAFSR_E_SYNDROME	(0x1ffUL << 0UL) /* ch,ch+,jp */
223 #define CHAFSR_E_SYNDROME_SHIFT	0UL
228  * interrupts are re-enabled to prevent multiple traps for the same error.  I.e.