Searched refs:SOC_RESET_CONTROL_CPU_WARM_RST_MASK (Results 1 – 7 of 7) sorted by relevance
94 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET macro293 = SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
164 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ macro
166 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ macro
131 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 macro132 #define SOC_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK) >> SO…133 …M_RST_SET(x) (((x) << SOC_RESET_CONTROL_CPU_WARM_RST_LSB) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
358 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ macro
451 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK\ macro
706 val |= SOC_RESET_CONTROL_CPU_WARM_RST_MASK; in hif_pci_device_warm_reset()